yosys

mirror of https://github.com/YosysHQ/yosys.git

Author	SHA1	Message	Date
Adam Izraelevitz	794cec0016	More progress on Firrtl backend. Chisel -> Firrtl -> Verilog -> Firrtl -> Verilog is successful for a simple rocket-chip design.	2017-02-13 11:17:53 -08:00
Adam Izraelevitz	f77dc3bacc	Bugfix: include assign to write-mask	2016-11-18 11:49:26 -08:00
Clifford Wolf	e01382739d	More progress in FIRRTL back-end	2016-11-18 02:41:29 +01:00
Clifford Wolf	c051115e03	Progress in FIRRTL back-end	2016-11-18 00:32:35 +01:00
Clifford Wolf	57966a619f	Added first draft of FIRRTL back-end	2016-11-17 23:36:47 +01:00