riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
14,280 Commits 92 Branches 49 Tags 38 MiB
Commit Graph

7 Commits

Author SHA1 Message Date
Lofty 8cc9aa7fc6 intel_alm: drop quartus support 2024-05-03 11:32:33 +01:00
Lofty 00b0e850db intel_alm: re-enable carry chains for ABC9 2023-05-25 18:28:10 +01:00
Lofty a31c8a82be intel_alm: preliminary Arria V support 2021-11-25 17:20:36 +01:00
gatecat 34a08750fa intel_alm: Fix illegal carry chains 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 22:37:06 +01:00
Dan Ravensloft 4d9d90079c intel_alm: add additional ABC9 timings 2020-07-23 11:57:07 +01:00
Dan Ravensloft 16a3048308 intel_alm: Documentation improvements 2020-04-21 19:38:15 +02:00
Dan Ravensloft 2e37e62e6b synth_intel_alm: alternative synthesis for Intel FPGAs 
By operating at a layer of abstraction over the rather clumsy Intel primitives,
we can avoid special hacks like `dffinit -highlow` in favour of simple techmapping.

This also makes the primitives much easier to manipulate, and more descriptive
(no more cyclonev_lcell_comb to mean anything from a LUT2 to a LUT6).
 2020-04-15 11:40:41 +02:00