8 Commits

Author	SHA1	Message	Date
Keith Rothman	3090951d54	Changes required for VPR place and route synth_xilinx. ... Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>	2019-03-01 12:02:27 -08:00
Clifford Wolf	6991c132b5	Add Xilinx RAM64X1D and RAM128X1D simulation models	2018-03-07 17:31:48 +01:00
Clifford Wolf	853e949c0e	Disabled (unused) Xilinx tristate buffers	2015-02-04 16:33:59 +01:00
Clifford Wolf	816fe6bbe0	Added Xilinx example for Basys3 board	2015-02-01 17:09:34 +01:00
Clifford Wolf	909a95182b	Fixed xilinx FDSE sim model	2015-01-24 11:03:22 +01:00
Clifford Wolf	7031231145	Added MUXCY and XORCY support to synth_xilinx	2015-01-17 15:39:54 +01:00
Clifford Wolf	fd8c8d4fd3	Added FF cells to xilinx/cells_sim.v	2015-01-16 14:59:40 +01:00
Clifford Wolf	38dfc5c580	added minimalistic xilinx sim models	2015-01-08 00:05:11 +01:00