riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
14,200 Commits 92 Branches 49 Tags 39 MiB
Commit Graph

14200 Commits

Author SHA1 Message Date
Miodrag Milanovic 834276a2f7 show: Add option to add cell/wire "src" attribute into graphviz attribute href 2024-02-14 09:50:53 +01:00
github-actions[bot] 91685355a0 Bump version 2024-02-14 00:15:26 +00:00
Martin Povišer b16f4900fd ast/simplify: Interpret hdlname w/o expecting backslash 2024-02-13 21:38:41 +01:00
Catherine d8ce26a5ba read_verilog: correctly format `hdlname` attribute value. 
The leading slash is not a part of the attribute as it only concerns
public values.
 2024-02-13 18:41:53 +00:00
Catherine 42920c9bc0 cxxrtl: rationalize `debug_items` accessors. 
Before this commit, `at()` and `operator[]` did the same thing, making
one of them redundant. There was also a somewhat awkward `parts_at()`,
which is more generic than `at()`.

After this commit, `parts_at()` becomes `at()`, and `at()` becomes
`operator[]`. Any quick-and-dirty accesses should use `items["name"]`,
which expects a single-part item. Generic code should instead use
`items.at("name")`, which will return multiple parts. Both will check
for the existence of the name.

This is unlikely to break downstream code since it's likely been using
the shorter `operator[]`. (In any case this API is not stable.)
 2024-02-13 15:13:53 +00:00
Catherine c3c44225de cxxrtl: document some `module` invariants. NFC 2024-02-13 15:13:53 +00:00
Catherine ae1a67ba47 cxxrtl: fix debug information for zero-width items. 
Because all objects in C++ must have non-zero size, a `value<0>` has
a size of 4 despite consisting of a `uint32_t chunks[0]`. The debug
item assertions were not written expecting that and prevent any debug
items for such values from compiling.

The C API does not define exactly what happens for a zero-width debug
item, but it seems OK to say that they should refer to some unique
pointer that cannot be, in actuality, read or written. This allows
some techniques or optimizations that use `curr` pointers as keys and
assume they correspond 1-to-1 to simulation objects.
 2024-02-13 15:13:41 +00:00
github-actions[bot] 606bbef30c Bump version 2024-02-13 00:16:18 +00:00
Jannis Harder 3473b6dd27
Merge pull request #4206 from povik/cli-crashes 
driver: Fix crashes on missing cli arguments
 2024-02-12 16:39:38 +01:00
Martin Povišer 54a97f8bb7 driver: Fix crashes on missing cli arguments 2024-02-12 14:56:23 +01:00
Miodrag Milanovic 353ccc9e58 do not override existing shell variable 2024-02-12 12:58:13 +01:00
Miodrag Milanovic ae7daf99f4 Verific: Add attributes to module instantiation 2024-02-12 09:53:47 +01:00
Miodrag Milanović edb95c69a9
Merge pull request #4084 from jix/scopeinfo 
$scopeinfo support
 2024-02-12 09:51:22 +01:00
Miodrag Milanovic 10297127be fix test for verific 2024-02-12 09:19:58 +01:00
passingglance 5226d07721
Update CHAPTER_CellLib.rst 
Fix parameter name to \WIDTH for $tribuf cell.
 2024-02-11 23:59:07 -08:00
github-actions[bot] cd8e6cbc64 Bump version 2024-02-12 00:16:18 +00:00
Dag Lem f09ea16bd1 Resolve struct member multiple dimensions defined in stages with typedef 2024-02-11 11:26:52 -05:00
Dag Lem fab326d3e8 Add multidimensional arrays to SystemVerilog features in README 2024-02-11 11:26:52 -05:00
Dag Lem a4ae773150 Added test for multidimensional packed arrays 2024-02-11 11:26:52 -05:00
Dag Lem 03f35c3def Resolve multiple dimensions defined in stages with typedef 2024-02-11 11:26:52 -05:00
Dag Lem e0d3977e19 Add support for $dimensions and $unpacked_dimensions 2024-02-11 11:26:52 -05:00
Dag Lem 2125357e76 Add support for $increment 2024-02-11 11:26:52 -05:00
Dag Lem 88d9e213cb Decoding of a few more AST nodes in dumpVlog 2024-02-11 11:26:52 -05:00
Dag Lem a32d9b6c45 Fix test of memory vs. memory converted to registers 
The purpose of memtest02 in tests/simple/memory.v is to	test bit
select on both memory (mem1) and memory converted to registers (mem2).

After 7cfae2c52, mem1 was automatically converted to registers,
and the test no longer worked as intended. This is fixed by
adding (* nomem2reg *) to mem1.
 2024-02-11 11:26:52 -05:00
Dag Lem 39fea32c6e Add support for packed multidimensional arrays 
* Generalization of dimensions metadata (also simplifies $size et al.)
* Parsing and elaboration of multidimensional packed ranges
 2024-02-11 11:26:52 -05:00
Jannis Harder ac0fb2e301
Merge pull request #4199 from tpwrules/test-fix 
tests/various/clk2fflogic_effects.sh: fix on macOS
 2024-02-11 02:32:42 +01:00
github-actions[bot] 0b835f28ca Bump version 2024-02-11 00:17:25 +00:00
Martin Povišer c46ebf28c2
Merge pull request #4198 from passingglance/patch-1 
Update CHAPTER_Basics.rst
 2024-02-10 23:16:30 +01:00
Thomas Watson 10e06f9b66 tests/various/clk2fflogic_effects.sh: remove /tmp use 
Might not be accessible.
 2024-02-10 15:09:54 -06:00
Thomas Watson b1f8308772 tests/various/clk2fflogic_effects.sh: fix tail invocation 
Previous syntax is a GNU extension and not accepted by macOS. Use
documented -n option instead, compatible with POSIX-compliant tail
implementations.
 2024-02-10 15:07:55 -06:00
passingglance 2b89a5cced
Update CHAPTER_Basics.rst 
Fix typo in Fig. 2.2 caption.
 2024-02-10 10:52:20 -08:00
github-actions[bot] 31dbd915ca Bump version 2024-02-10 00:15:13 +00:00
Ethan Mahintorabi 8566489d85
stat: Add sequential area output to stat -liberty 
Checks to see if a cell is of type ff in the liberty,
and keeps track of an additional area value.

```
   Chip area for module '\addr': 92.280720
   Sequential area for module '\addr': 38.814720
```

Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
 2024-02-09 23:51:00 +00:00
Miodrag Milanovic 46838172c2 Next dev cycle 2024-02-09 08:19:14 +01:00
Miodrag Milanovic 543faed9c8 Release version 0.38 2024-02-09 08:16:24 +01:00
github-actions[bot] 8e3a718e30 Bump version 2024-02-09 00:15:19 +00:00
Miodrag Milanović 2f4c917dac
Merge pull request #4181 from povik/ci-cxxstd-fix 
ci: Fix CXXSTD typo
 2024-02-08 18:55:47 +01:00
Miodrag Milanović d808258583
Merge pull request #4193 from povik/opt_lut-help 
opt_lut: Remove leftover `-dlogic` help
 2024-02-08 18:54:16 +01:00
Martin Povišer 043f1e2bcb opt_lut: Remove leftover `-dlogic` help 2024-02-08 17:49:44 +01:00
Martin Povišer af1a5cfeb9 Address `SigBit`/`SigSpec` confusion issues under c++20 2024-02-08 17:48:36 +01:00
Martin Povišer 66479a2232 hashlib: Add missing `stdint.h` include 
We use `uint32_t` `uint64_t` etc. so add an explicit include.
 2024-02-08 14:27:12 +00:00
Catherine 1236bb65b6 read_verilog: don't include empty `opt_sva_label` in span. 
Consider this SystemVerilog file:

    module top(...);
      input clk;
      input [7:0] data;
      input ack;

      always @(posedge clk)
        if (ack) begin
          assert(data != 8'h0a);
        end
    endmodule

Before this commit, the span for the assert was:

        if (ack) begin>
          assert(data != 8'h0a)<;

After this commit, the span for the assert is:

        if (ack) begin
          >assert(data != 8'h0a)<;

This helps editor integrations that only look at the beginning
of the span.
 2024-02-08 14:25:35 +00:00
Miodrag Milanović 675b8a7319
Merge pull request #4190 from YosysHQ/xdg 
Follow the XDG Base Directory Specification
 2024-02-08 14:05:31 +01:00
Miodrag Milanovic a38273c19d add log_suppressed and fixed formatting 2024-02-08 12:19:42 +01:00
Martin Povišer a1824ba5b6
Merge pull request #4187 from povik/synth-help 
synth: Run script in full in help mode
 2024-02-08 09:56:48 +01:00
Miodrag Milanovic 2797d67569 Move block and change message to debug 2024-02-08 09:19:19 +01:00
Miodrag Milanovic f785eef685 Merge branch 'master' of github.com:hakan-demirli/yosys into xdg 2024-02-08 09:03:52 +01:00
Martin Povišer 862f2fd705 proc_dlatch: Include `$bwmux` among considered mux cells 2024-02-08 00:08:50 +01:00
Martin Povišer 7a3316dd78 synth: Tweak phrasing of `-booth` help 2024-02-08 00:05:15 +01:00
Martin Povišer a98d363d9d synth: Run script in full in help mode 2024-02-08 00:05:15 +01:00