riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
3,101 Commits 76 Branches 48 Tags 62 MiB
Commit Graph

112 Commits

Author SHA1 Message Date
Clifford Wolf a6750b3753 Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem) 2014-02-03 13:01:45 +01:00
Clifford Wolf 67b0ce2578 Only generate write-enable $and if WE is not constant 1 in memory_map 2014-02-02 21:27:26 +01:00
Clifford Wolf f3154f5694 Added automatic memid generation to memory_unpack command 2014-01-17 00:15:15 +01:00
Clifford Wolf 4d8318ad1b Added memory_unpack command 2014-01-17 00:05:02 +01:00
Clifford Wolf fb2bf934dc Added correct handling of $memwr priority 2014-01-03 00:22:17 +01:00
Clifford Wolf 93a70959f3 Replaced RTLIL::Const::str with generic decoder method 2013-12-04 14:14:05 +01:00
Clifford Wolf 97efc2ed5f A fix in memory_dff for write ports with static addresses 2013-12-01 14:08:18 +01:00
Clifford Wolf 888c43210b Fixed help message typo (memory pass) 2013-10-30 00:47:31 +01:00
Clifford Wolf 95dbacefbf Fixed bug in synthesis of memories that are never written 2013-10-17 21:00:37 +02:00
Clifford Wolf 8d37d1e08b Added -nomap option to memory pass 2013-03-21 09:11:06 +01:00
Clifford Wolf f3a849512f Added help messages to memory_* passes 2013-03-01 10:17:35 +01:00
Clifford Wolf 7764d0ba1d initial import 2013-01-05 11:13:26 +01:00