riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
8,206 Commits 89 Branches 51 Tags 38 MiB
Commit Graph

4 Commits

Author SHA1 Message Date
Eddie Hung a5764a1236 Disable RAM16X1D test 2019-12-13 10:28:13 -08:00
Eddie Hung d0ee4cd88f Remove extraneous synth_xilinx call 2019-12-12 19:00:26 -08:00
Eddie Hung 01116f0f0a Add tests for these new models 2019-12-12 18:52:48 -08:00
Eddie Hung caab66111e Rename memory tests to lutram, add more xilinx tests 2019-12-12 17:44:37 -08:00