Commit Graph

10 Commits

Author SHA1 Message Date
Krystine Sherwin 50d8c1b258
First pass example_synth done
Split coarse grain representation into 4 parts, loosely: fsm/opt, other optimizations/techmap/memory_dff, DSPs, alumacc/memory -nomap.
Split hardware mapping into subsections as well: memory blocks (map_ram and map_ffram), arithmetic (map_gates), FFs (map_ffs), LUTs (map_luts and briefly abc), and other (map_cells and a note on hilomap and iopadmap).

Also add `-T` flag to Yosys call to remove footer from log output.
2023-12-20 14:08:06 +13:00
Krystine Sherwin a33b1b6059
More work on example_synth
Added highlighting in (most) schematics.
Written down to end of coarse-grain, with a couple of TODOs for filling in gaps.
Includes `techmap_synth.rst` stub.
2023-12-18 17:49:15 +13:00
Krystine Sherwin 742ec78ca3
Switching example synth to fifo
Fifo code based on SBY quick start.
Instead of showing the full design we are (currently) focusing on a single output (rdata), using `%ci*` to get the subcircuit it relies on.
2023-12-18 13:19:01 +13:00
Krystine Sherwin 80c78aaad6
New example_synth code
`example_synth.rst` updated down to coarse-grain representation.
2023-12-14 16:21:52 +13:00
Krystine Sherwin 6d1caf6134
Initial synth_ice40 example
Overall structure in place to match the iCE40 flow.
Still needs a new example design, and more text for the later sections (which the counter doesn't cover).
2023-12-14 11:33:32 +13:00
Krystine Sherwin e34a25ea27
TODOs
Blocking tasks are now capital TODO (compared to non-blocking todo).
Updated some of the todos.
Added note about which intel synth does which families.
Rename extended Yosys universe to Yosys family.
Added brief text to landing page, and also a note about the restructure and where to find old docs.
Moved todolist above ToC in preparation for disabling it in the config (so that it doesn't need it's own header).

Fixed pdf build, was previously breaking on trying to include the svg badges.
2023-12-12 12:05:45 +13:00
Krystine Sherwin f949579cf3
Testing latexpdf build
Also added `seealso` blocks to example synth.
2023-12-08 11:19:12 +13:00
Krystine Sherwin aef9921fc9
Tidying TODOs 2023-12-08 09:50:10 +13:00
Krystine Sherwin 1e3b90ae56
Removing typical phases doc
Moved remaining content into relevant places.
Added `load_design.rst` to more scripting.
Split fsm handling and abc out of optimization passes. Also moved things around to match the general flow previously described.
Changed generic `synth` for `prep` instead.
2023-12-07 17:14:21 +13:00
Krystine Sherwin f9ce3d1c26
WIP merging synth phases with example
Replace `typical_phases.rst` and `examples.rst` with a single `example_synth.rst`.
Also updating the counter example to match.

Aims to reduce redundancy, and simplify the getting started section.
Details on things like `proc`, `memory` and `fsm` should instead be in the advanced section (under the new `synth` subsection).
2023-12-07 13:04:46 +13:00