yosys

Commit Graph

Author	SHA1	Message	Date
Krystine Sherwin	50d8c1b258	First pass example_synth done Split coarse grain representation into 4 parts, loosely: fsm/opt, other optimizations/techmap/memory_dff, DSPs, alumacc/memory -nomap. Split hardware mapping into subsections as well: memory blocks (map_ram and map_ffram), arithmetic (map_gates), FFs (map_ffs), LUTs (map_luts and briefly abc), and other (map_cells and a note on hilomap and iopadmap). Also add `-T` flag to Yosys call to remove footer from log output.	2023-12-20 14:08:06 +13:00
Krystine Sherwin	742ec78ca3	Switching example synth to fifo Fifo code based on SBY quick start. Instead of showing the full design we are (currently) focusing on a single output (rdata), using `%ci*` to get the subcircuit it relies on.	2023-12-18 13:19:01 +13:00

Author

SHA1

Message

Date

Krystine Sherwin

50d8c1b258

First pass example_synth done

Split coarse grain representation into 4 parts, loosely: fsm/opt, other optimizations/techmap/memory_dff, DSPs, alumacc/memory -nomap.
Split hardware mapping into subsections as well: memory blocks (map_ram and map_ffram), arithmetic (map_gates), FFs (map_ffs), LUTs (map_luts and briefly abc), and other (map_cells and a note on hilomap and iopadmap).

Also add `-T` flag to Yosys call to remove footer from log output.

2023-12-20 14:08:06 +13:00

Krystine Sherwin

742ec78ca3

Switching example synth to fifo

Fifo code based on SBY quick start.
Instead of showing the full design we are (currently) focusing on a single output (rdata), using `%ci*` to get the subcircuit it relies on.

2023-12-18 13:19:01 +13:00

2 Commits