yosys

Author	SHA1	Message	Date
Miodrag Milanovic	1ecf6aee9b	Test fixes for latest iverilog	2022-09-21 15:46:43 +02:00
Tristan Gingold	c25f3ff3df	sf2: suport $alu gate and ARI1 implementation	2022-08-31 08:40:44 +02:00
Tristan Gingold	39993a92d7	sf2/cells_sim.v: add XTLOSC, SYSRESET cells	2022-08-31 08:40:44 +02:00
Tristan Gingold	1c0119aa90	sf2/cells_sim.v: add IOSTD parameter to I/O cells This parameter is set by LiberoSoc IPs, so it is needed to avoid errors when using those IPs.	2022-08-31 08:40:43 +02:00
Stefan Riesenberger	a58571d0fe	sf2: fix name of AND modules	2021-04-09 16:46:05 +02:00
Dan Ravensloft	7dc0439de4	sf2: replace sf2_iobs with {clkbuf,iopad}map	2020-07-09 21:28:52 +01:00
Clifford Wolf	350dfd3745	Add link to SF2 / igloo2 macro library guide Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-03-07 09:08:26 -08:00
Clifford Wolf	8b0719d1e3	Improvements in sf2 cells_sim.v Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-03-06 16:18:49 -08:00
Clifford Wolf	78762316aa	Refactor SF2 iobuf insertion, Add clkint insertion Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-03-06 00:41:02 -08:00
Clifford Wolf	db5765b443	Add SF2 IO buffer insertion Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-01-17 14:38:37 +01:00
Clifford Wolf	d084fb4c3f	Fix sf2 LUT interface Signed-off-by: Clifford Wolf <clifford@clifford.at>	2018-10-31 15:36:53 +01:00
Clifford Wolf	cf79fd4376	Basic SmartFusion2 and IGLOO2 synthesis support Signed-off-by: Clifford Wolf <clifford@clifford.at>	2018-10-31 15:28:57 +01:00