Commit Graph

5 Commits

Author SHA1 Message Date
whitequark 8d712b1095 cxxrtl: handle multipart signals.
This avoids losing design visibility when using the `splitnets` pass.
2020-06-11 19:34:35 +00:00
whitequark fa04b19670 cxxrtl: expose RTLIL::{Wire,Memory}->start_offset in debug info. 2020-06-11 12:43:17 +00:00
whitequark 0955a603c8 cxxrtl: disambiguate values/wires and their aliases in debug info.
With this change, it is easier to see which signals carry state (only
wire<>s appear as `reg` in VCD files) and to construct a minimal
checkpoint (CXXRTL_WIRE debug items represent the canonical smallest
set of state required to fully reconstruct the simulation).
2020-06-10 14:39:45 +00:00
whitequark f2d7a18756 cxxrtl: emit debug information for constant wires.
Constant wires can represent a significant chunk of the design in
generic designs or after optimization. Emitting them in VCD files
significantly improves usability because gtkwave removes all traces
that are not present in the VCD file after reload, and iterative
development suffers if switching a varying signal to a constant
disrupts the workflow.
2020-06-08 17:29:08 +00:00
whitequark c399359ed6 cxxrtl: add a C API for driving and introspecting designs.
Compared to the C++ API, the C API currently has two limitations:
  1. Memories cannot be updated in a race-free way.
  2. Black boxes cannot be implemented in C.
2020-06-06 21:12:55 +00:00