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5 Commits

Author SHA1 Message Date
Marcelina Kościelnicka 18806f1ef6 memory_bram: Reuse extract_rdff helper for make_outreg. 
Also properly skip read ports with init value or reset when not making
use of make_outreg.  Proper support for matching those will land later.
 2021-05-25 22:42:03 +02:00
gatecat eb106732d9 intel_alm: Add global buffer insertion 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 22:37:06 +01:00
gatecat 5dba138c87 intel_alm: Add IO buffer insertion 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 22:37:06 +01:00
Dan Ravensloft 0d4c2f0a65 intel_alm: add Cyclone 10 GX tests 2020-07-05 21:36:38 +02:00
Dan Ravensloft 5b779f7f4e intel_alm: direct LUTRAM cell instantiation 
By instantiating the LUTRAM cell directly, we avoid a trip through
altsyncram, which speeds up Quartus synthesis time. This also gives
a little more flexibility, as Yosys can build RAMs out of individual
32x1 LUTRAM cells.

While working on this, I discovered that the mem_init0 parameter of
<family>_mlab_cell gets ignored by Quartus.
 2020-05-07 21:03:13 +02:00