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14044 Commits

Author SHA1 Message Date
Emil J 0dfa4962d1
Merge pull request #4547 from leviathanch/fix_apicula1 
Add DQS and related primitives to Gowin tech files
 2024-08-19 15:44:48 +02:00
Emil J. Tywoniak 4847caac49 driver: print maximum memory usage on macOS as well 2024-08-19 12:50:12 +02:00
Krystine Sherwin 6df0c3d9ec
docs: Fix synth_flow generation 2024-08-19 21:25:51 +12:00
Krystine Sherwin 8773cf7721
test-verific: Use fast runner 2024-08-19 21:24:48 +12:00
N. Engelhardt 7f08a298a4
Merge pull request #4542 from YosysHQ/krys/rtd 
Local readthedocs
 2024-08-19 10:04:38 +02:00
David Lanzendörfer d1b767ea8b Adding missing to Gowin tech files 
Without OSER4_MEM, IDES4_MEM and DQS the synthesis of my Rocket Chip
design for my Sipeed Tang FPGA fails.
 2024-08-18 19:38:31 +01:00
NachtSpyder04 aa60255e0e update help messages that went beyond line length limit 2024-08-18 20:27:35 +05:30
Saish Karole 34aabd56cc
Apply suggestions from code review 
Co-authored-by: Martin Povišer <povik@cutebit.org>
 2024-08-18 20:12:53 +05:30
Saish Karole d80d4dc51c
[Docs]:Add new cell type help messages (#1) 
* add shift operators description

* update shift operations' descriptions, add desciptions for add, sub, logic_*, tribuf, mux, demux, concat, pow and comparison operators
 2024-08-17 15:47:00 +05:30
github-actions[bot] 5fb3c0b1d9 Bump version 2024-08-17 00:17:44 +00:00
KrystalDelusion 3dd32d741a Stop unconditionally building abc 
_What are the reasons/motivation for this change?_
abc builds unconditional because `check-git-abc` is a phony prerequisite and therefore always runs, and since it always runs it will always trigger abc to rebuild.

_Explain how this is achieved._
Convert `check-git-abc` to an order-only prerequisite.  It still runs as before, but no longer triggers yosys-abc to rebuild when it does.

_If applicable, please suggest to reviewers how they can test the change._
 2024-08-17 11:04:17 +12:00
Krystine Sherwin e9f909aa25
minisat: Record changes in patch 2024-08-17 10:01:25 +12:00
Krystine Sherwin 7bd3c7b968
Fix test-verific.yml 2024-08-16 10:43:51 +12:00
Krystine Sherwin 3b63ab07ae
docs: Build RTD artifacts directly 
Use rtds-action instead of yosys-cmd-ref repo.
Add rtds_action to docs configuration.
Add `.readthedocs.yaml`.
Update `DOCS_USAGE_` make target to be able to use pre-generated executables without forcing a remake.
 2024-08-16 10:43:51 +12:00
Krystine Sherwin 55307a5452
minisat: Check for gcc 2024-08-16 04:30:37 +12:00
Krystine Sherwin eb02ab07da
minisat: Use reallocarray 
Avoid gcc warning about non-trivial copying.
 2024-08-16 04:30:37 +12:00
Krystine Sherwin d34833d177
Better snprintf size handling 2024-08-16 04:30:37 +12:00
Krystine Sherwin 636ce9ac2c
snprintf 2024-08-16 04:30:36 +12:00
Krystine Sherwin 7b47f645d7
Address warnings 
- Setting default values
- Fixing mismatched types
- Guarding unused var
 2024-08-16 04:30:31 +12:00
Miodrag Milanovic 54d237ff82 add min_ce_use and min_srst_use parameters 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 14e43139cb Run opt_merge, helps with inverted reset/load signals 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 220ddeac4d Set -mince and -minsrst 2024-08-15 17:50:36 +02:00
Miodrag Milanovic dbf1d037e8 Cleanup 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 7bf623a0c7 Fix simulation model warnings 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 3848563600 Update tests 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 262ad03cd3 Add iopads by default add option to disable and keep old one for compatibility 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 8f806c0d12 Added DDFR support 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 1a6e5c671f Add meminit handling for NX_RFB_U 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 6876a27547 Add NX_DFR simulation model 2024-08-15 17:50:36 +02:00
Miodrag Milanovic eb30be6189 Impulse does not support these types but NG-ULTRA architecture does 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 7601dc740b Some memory types are only supported on NG-LARGE 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 4372487a6f raw must be 16 bits for nx tools to work 2024-08-15 17:50:36 +02:00
Miodrag Milanovic f8ae93c0ea run setundef for all x inputs 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 40f05009e3 Fix CY chaining and CI injection 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 596506b88b Add NX_XCDC_U to wrappers 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 8909a42796 Better wire check 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 5766555642 Support brams with initialization 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 4aaab8f395 start adding wfg model 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 41a86fdb2c fix 2024-08-15 17:50:36 +02:00
Miodrag Milanovic f4d8ea4c40 Start adding RFB simulation models 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 8eb099c1f4 remove debug attribute 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 829dd62054 block ram mapping for standard modes 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 9d6b47466f Add RF initialization 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 7e4aef06e4 Add register file mapping 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 11449ec493 Cleanup not connected ports 2024-08-15 17:50:36 +02:00
Miodrag Milanovic f9f68c3cd1 Split sim models into multiple files and implement few 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 04d3672121 No need for LOC 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 41ae513d60 support other I/O configurations 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 34f08bc639 Enable nanoxplore tests 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 645888cff5 cleanup 2024-08-15 17:50:36 +02:00