riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
12,898 Commits 92 Branches 49 Tags 39 MiB
Commit Graph

246 Commits

Author SHA1 Message Date
Miodrag Milanovic 0ccff57062 Next dev cycle 2023-12-05 08:58:28 +01:00
Miodrag Milanovic 8f07a0d840 Release version 0.36 2023-12-05 08:55:12 +01:00
Jannis Harder 6cf50d16a8
Merge pull request #3973 from anonkey/master 
cli(tcl): add ability to pass argument to tcl script from cli
 2023-11-13 16:29:05 +01:00
Miodrag Milanovic 8808da243b Next dev cycle 2023-11-07 08:47:34 +01:00
Miodrag Milanovic cc31c6ebc4 Release version 0.35 2023-11-07 08:45:31 +01:00
anonkey ea91f189a3
cli(tcl): add ability to pass argument to tcl script from cli 2023-11-03 12:21:35 +01:00
Miodrag Milanovic b88f7fc6e8 Next dev cycle 2023-10-05 09:16:05 +02:00
Miodrag Milanovic 4a1b559925 Release version 0.34 2023-10-05 09:14:12 +02:00
Zachary Snow 4edb1a1921 sv: support assignments within expressions 
- Add support for assignments within expressions, e.g., `x[y++] = z;` or
  `x = (y *= 2) - 1;`. The logic is handled entirely within the parser
  by injecting statements into the current procedural block.
- Add support for pre-increment/decrement statements, which are
  behaviorally equivalent to post-increment/decrement statements.
- Fix non-standard attribute position used for post-increment/decrement
  statements.
 2023-09-05 22:27:55 -04:00
Miodrag Milanovic 11a2de815a Next dev cycle 2023-09-05 08:11:03 +02:00
Miodrag Milanovic 2584903a06 Release version 0.33 2023-09-05 08:08:51 +02:00
Miodrag Milanovic 105c447010 Next dev cycle 2023-08-07 08:25:37 +02:00
Miodrag Milanovic fbab08acf1 Release version 0.32 2023-08-07 08:22:52 +02:00
Miodrag Milanovic 4fff228b0c Next dev cycle 2023-07-18 08:47:52 +02:00
Miodrag Milanovic f3c6b41050 Release version 0.31 2023-07-18 08:45:00 +02:00
Miodrag Milanovic c5e4eec3ba Next dev cycle 2023-06-06 09:41:26 +02:00
Miodrag Milanovic f7a8284c7b Release version 0.30 2023-06-06 09:38:46 +02:00
Miodrag Milanovic f790e00478 Next dev cycle 2023-05-09 08:00:06 +02:00
Miodrag Milanovic 9c5a60eb20 Release version 0.29 2023-05-09 07:57:55 +02:00
Miodrag Milanovic d0855576ae Next dev cycle 2023-04-14 09:54:46 +02:00
Miodrag Milanovic 0d6f4b0683 Release version 0.28 2023-04-14 09:52:15 +02:00
Miodrag Milanovic 368f2984cd Next dev cycle 2023-03-06 08:50:14 +01:00
Miodrag Milanovic 5f88c218b5 Release version 0.27 2023-03-06 08:47:51 +01:00
Miodrag Milanovic a7099b0a72 Next dev cycle 2023-02-08 12:34:19 +01:00
Miodrag Milanovic 7e588664e7 Release version 0.26 2023-02-08 12:32:43 +01:00
Miodrag Milanovic 5f33c0e0b2 Updated changelog 2023-02-08 10:11:47 +01:00
Miodrag Milanovic 4fc5207b1e Add deprecation info to changelog 2023-01-11 11:23:23 +01:00
Miodrag Milanovic c34d308bbd Next dev cycle 2023-01-03 09:36:13 +01:00
Miodrag Milanovic e02b7f64bc Release version 0.25 2023-01-03 09:34:45 +01:00
Miodrag Milanovic f1da4b0204 Next dev cycle 2022-12-05 17:21:20 +01:00
Miodrag Milanovic 313b7997b5 Release version 0.24 2022-12-05 17:11:03 +01:00
Jannis Harder 239ecf9185 Merge branch 'zachjs-master' 2022-11-21 17:47:43 +01:00
Miodrag Milanovic cb7299c3dc Next dev cycle 2022-11-08 07:57:48 +01:00
Miodrag Milanovic 7ce5011c24 Release version 0.23 2022-11-08 07:55:31 +01:00
Miodrag Milanovic cff42f0af5 Update CHANGELOG 2022-11-07 13:16:38 +01:00
Miodrag Milanovic 9470ef9efe Update CHANGELOG 2022-11-07 12:13:19 +01:00
Zachary Snow 71e7e09092 verilog: Support module-scoped task/function calls 
This is primarily intended to enable the standard-permitted use of
module-scoped identifiers to refer to tasks and non-constant functions.
As a side-effect, this also adds support for the non-standard use of
module-scoped identifiers referring to constant functions, a feature
that is supported in some other tools, including Iverilog.
 2022-10-29 15:14:11 -04:00
Jannis Harder ac906d15ce Add YOSYS_ABORT_ON_LOG_ERROR environment variable for debugging. 2022-10-07 15:02:33 +02:00
Miodrag Milanovic a5172df9e9 Next dev cycle 2022-10-05 11:32:11 +02:00
Miodrag Milanovic f109fa3d4c Release version 0.22 2022-10-05 11:30:38 +02:00
Miodrag Milanovic 7db26a8e59 Update CHANGELOG 2022-10-05 11:28:48 +02:00
Miodrag Milanovic 07d9924a1b Next dev cycle 2022-09-06 08:26:44 +02:00
Miodrag Milanovic e6d2a900a9 Release version 0.21 2022-09-06 08:23:30 +02:00
Miodrag Milanovic 0ff129c10b Update Changelog 2022-09-06 08:22:23 +02:00
Jannis Harder f7023d06a2 sim: -hdlname option to preserve flattened hierarchy in sim output 2022-08-16 13:37:30 +02:00
Jannis Harder 65145db7e7 rename: Add -witness mode 2022-08-16 13:37:30 +02:00
Jannis Harder efd5b86eb9 aiger: Add yosys-witness support 
Adds a new json based aiger map file and yosys-witness converters to us
this to convert between native and AIGER witness files.
 2022-08-16 13:37:30 +02:00
Jannis Harder f041e36c6e smtbmc: Add native json based witness format + smt2 backend support 
This adds a native json based witness trace format. By having a common
format that includes everything we support, and providing a conversion
utility (yosys-witness) we no longer need to implement every format for
every tool that deals with witness traces, avoiding a quadratic
opportunity to introduce subtle bugs.

Included:

  * smt2: New yosys-smt2-witness info lines containing full hierarchical
    paths without lossy escaping.
  * yosys-smtbmc --dump-yw trace.yw: Dump results in the new format.
  * yosys-smtbmc --yw trace.yw: Read new format as constraints.
  * yosys-witness: New tool to convert witness formats.
    Currently this can only display traces in a human-readable-only
    format and do a passthrough read/write of the new format.
  * ywio.py: Small python lib for reading and writing the new format.
    Used by yosys-smtbmc and yosys-witness to avoid duplication.
 2022-08-16 13:37:30 +02:00
Jannis Harder a2f9ebe43a memory_map: Add -formal option 
This maps memories for a global clock based formal verification flow.
This implies -keepdc, uses $ff cells for ROMs and sets hdlname
attributes.
 2022-08-16 13:37:30 +02:00
Jannis Harder c0063288d6 Add the $anyinit cell and the formalff pass 
These can be used to protect undefined flip-flop initialization values
from optimizations that are not sound for formal verification and can
help mapping all solver-provided values in witness traces for flows that
use different backends simultaneously.
 2022-08-16 13:37:30 +02:00