mirror of https://github.com/YosysHQ/yosys.git
Release version 0.32
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@ -2,8 +2,15 @@
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List of major changes and improvements between releases
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=======================================================
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Yosys 0.31 .. Yosys 0.32-dev
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Yosys 0.31 .. Yosys 0.32
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--------------------------
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* Verific support
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- Added sub option "-lib" to reading commands for VHDL and
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SystemVerilog, that will later import all units/modules from
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marked files as blackboxes.
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* Various
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- Added support for $lt, $le, $gt, $ge to the code generating AIGs.
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Yosys 0.30 .. Yosys 0.31
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--------------------------
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4
Makefile
4
Makefile
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@ -141,7 +141,7 @@ LDLIBS += -lrt
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endif
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endif
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YOSYS_VER := 0.31+49
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YOSYS_VER := 0.32
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# Note: We arrange for .gitcommit to contain the (short) commit hash in
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# tarballs generated with git-archive(1) using .gitattributes. The git repo
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@ -157,7 +157,7 @@ endif
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OBJS = kernel/version_$(GIT_REV).o
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bumpversion:
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sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline f3c6b41.. | wc -l`/;" Makefile
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# sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline f3c6b41.. | wc -l`/;" Makefile
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# set 'ABCREV = default' to use abc/ as it is
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#
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