Ruben Undheim
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79cbf9067c
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Corrected spelling mistakes found by lintian
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2014-09-06 08:47:06 +02:00 |
Clifford Wolf
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3a7d5d188d
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Don't change existing binary FSM encoding if it is already optimal
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2014-08-30 14:43:06 +02:00 |
Clifford Wolf
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28cf48e31f
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Some improvements in FSM mapping and recoding
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2014-08-14 11:22:45 +02:00 |
Clifford Wolf
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10e5791c5e
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Refactoring: Renamed RTLIL::Design::modules to modules_
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2014-07-27 11:18:30 +02:00 |
Clifford Wolf
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4c4b602156
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Refactoring: Renamed RTLIL::Module::cells to cells_
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2014-07-27 01:51:45 +02:00 |
Clifford Wolf
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91704a7853
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Merged a few fixes for non-posix systems from github.com/Siesh1oo/yosys
(see https://github.com/cliffordwolf/yosys/pull/28)
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2014-03-11 14:24:24 +01:00 |
Clifford Wolf
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93a70959f3
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Replaced RTLIL::Const::str with generic decoder method
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2013-12-04 14:14:05 +01:00 |
Clifford Wolf
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66bc46b30b
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Improved FSM one-hot encoding, added binary encoding
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2013-05-24 14:39:19 +02:00 |
Clifford Wolf
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a338d1a082
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Added help messages for fsm_* passes
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2013-03-01 12:35:12 +01:00 |
Clifford Wolf
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7764d0ba1d
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initial import
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2013-01-05 11:13:26 +01:00 |