6 Commits

Author	SHA1	Message	Date
Dan Ravensloft	09ecb9b2cf	intel_alm: direct M10K instantiation	2020-07-05 23:28:59 +02:00
Dan Ravensloft	b004f09018	intel_alm: DSP inference	2020-07-05 05:39:20 +02:00
Dan Ravensloft	83cde2d02b	intel_alm: ABC9 sequential optimisations	2020-07-04 19:45:10 +02:00
Dan Ravensloft	5b779f7f4e	intel_alm: direct LUTRAM cell instantiation ... By instantiating the LUTRAM cell directly, we avoid a trip through altsyncram, which speeds up Quartus synthesis time. This also gives a little more flexibility, as Yosys can build RAMs out of individual 32x1 LUTRAM cells. While working on this, I discovered that the mem_init0 parameter of <family>_mlab_cell gets ignored by Quartus.	2020-05-07 21:03:13 +02:00
Dan Ravensloft	4ca5f9799b	intel_alm: cleanup duplication	2020-04-24 11:26:48 +02:00
Dan Ravensloft	2e37e62e6b	synth_intel_alm: alternative synthesis for Intel FPGAs ... By operating at a layer of abstraction over the rather clumsy Intel primitives, we can avoid special hacks like `dffinit -highlow` in favour of simple techmapping. This also makes the primitives much easier to manipulate, and more descriptive (no more cyclonev_lcell_comb to mean anything from a LUT2 to a LUT6).	2020-04-15 11:40:41 +02:00