6 Commits

Author	SHA1	Message	Date
N. Engelhardt	3c5b0ab164	fix test setup for synth_quicklogic memory tests	2023-12-04 15:52:03 +01:00
Krystine Sherwin	509d176523	attempting to sim split memory tests ... and failing	2023-12-04 15:52:03 +01:00
Krystine Sherwin	0d1668c1ee	QLF_TDP36K: asymmetric simulation tests	2023-12-04 15:52:03 +01:00
Krystine Sherwin	497cd021af	QLF_TDP36K: truncation tests matter ... Expected values are now stored in full precision rather than truncating to the same value as the input. i.e. 0x5a5a5a5a will truncate to 0x5a5a for write data but will remain 0x5a5a5a5a for expected read.	2023-12-04 15:52:03 +01:00
Krystine Sherwin	7f12d0ba95	QLF_TDP36K: more basic tdp/sdp sim tests ... Adds TDP submodule to generator. Adds shorthand expected signal to testbench (mostly to make it easier when I look at the vcd dump to figure out what I did wrong in tests).	2023-12-04 15:52:03 +01:00
Krystine Sherwin	3d08ed216d	QLF_TDP36K: parameterised sim test gen ... Also limited to 16 tests per file to allow parallelism. Previous tests are converted to new test format with no sim test steps.	2023-12-04 15:52:03 +01:00