riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
14,293 Commits 75 Branches 48 Tags 60 MiB
Commit Graph

3 Commits

Author SHA1 Message Date
Jannis Harder d6c7aa0e3d sim/formalff: Clock handling for yw cosim 2023-01-11 18:07:16 +01:00
Jannis Harder 7ddec5093f sim: Improvements and fixes for yw cosim 
* Fixed $cover handling
  * Improved sparse memory handling when writing traces
  * JSON summary output
 2023-01-11 18:07:16 +01:00
Jannis Harder 1494cfff00 New kernel/yw.{h,cc} to support reading Yosys witness files 
This contains parsing code as well as generic routines to associate the
hierarchical signals paths within a Yosys witness file to a loaded RTLIL
design, including support for memories.
 2023-01-11 18:07:16 +01:00