yosys

Commit Graph

Author	SHA1	Message	Date
Dan Ravensloft	0d4c2f0a65	intel_alm: add Cyclone 10 GX tests	2020-07-05 21:36:38 +02:00
Dan Ravensloft	5b779f7f4e	intel_alm: direct LUTRAM cell instantiation By instantiating the LUTRAM cell directly, we avoid a trip through altsyncram, which speeds up Quartus synthesis time. This also gives a little more flexibility, as Yosys can build RAMs out of individual 32x1 LUTRAM cells. While working on this, I discovered that the mem_init0 parameter of <family>_mlab_cell gets ignored by Quartus.	2020-05-07 21:03:13 +02:00

Author

SHA1

Message

Date

Dan Ravensloft

0d4c2f0a65

intel_alm: add Cyclone 10 GX tests

2020-07-05 21:36:38 +02:00

Dan Ravensloft

5b779f7f4e

intel_alm: direct LUTRAM cell instantiation

By instantiating the LUTRAM cell directly, we avoid a trip through
altsyncram, which speeds up Quartus synthesis time. This also gives
a little more flexibility, as Yosys can build RAMs out of individual
32x1 LUTRAM cells.

While working on this, I discovered that the mem_init0 parameter of
<family>_mlab_cell gets ignored by Quartus.

2020-05-07 21:03:13 +02:00

2 Commits