riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
7,925 Commits 81 Branches 48 Tags 64 MiB
Commit Graph

5 Commits

Author SHA1 Message Date
Diego H 266993408a Refactoring memory attribute matching based on IEEE 1364.1 and Tool specific 2019-12-13 15:43:24 -06:00
Diego H 751a18d7e9 Fixing citation in xc7_xcu_brams.txt file. Fixing RAMB36E1 test. 2019-12-12 17:32:58 -06:00
Diego H 937ec1ee78 Updating RAMB36E1 thresholds. Adding test for both RAMB18E1/RAMB36E1 2019-12-12 13:50:36 -06:00
Diego H 3a5a65829c Adjusting Vivado's BRAM min bits threshold for RAMB18E1 2019-11-27 12:05:04 -06:00
David Shah 6769d31ddb xilinx: Add support for UltraScale[+] BRAM mapping 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-23 11:47:37 +01:00