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8 Commits

Author SHA1 Message Date
Emil J. Tywoniak 838eb9c280 hashlib: acc -> eat 2024-11-26 10:52:07 +01:00
Emil J. Tywoniak 898d042604 hashlib: redo interface for flexibility 2024-11-26 10:52:07 +01:00
Emily Schmidt 9b5e81b13f drivertools: fix C++20 "incomplete type" error by moving constructors below other definitions 2024-08-22 10:40:56 +01:00
Emily Schmidt 79a1b691ea silence some more warnings, undo mistaken addition 2024-08-21 11:04:11 +01:00
Emily Schmidt 8f77494263 silence some warnings 2024-08-21 11:04:11 +01:00
Emily Schmidt 7b29d177ac add support for memories to c++ and smtlib functional backends 2024-08-21 11:01:09 +01:00
Jannis Harder d90268f610 fixup! drivertools: Utility code for indexing and traversing signal drivers 2024-08-21 11:01:09 +01:00
Jannis Harder 56572978f5 drivertools: Utility code for indexing and traversing signal drivers 
It adds `DriveBit`, `DriveChunk` and `DriveSpec` types which are similar
to `SigBit`, `SigChunk` and `SigSpec` but can also directly represent
cell ports, undriven bits and multiple drivers. For indexing an RTLIL
module and for querying signal drivers it comes with a `DriverMap` type
which is somewhat similar to a `SigMap` but is guaranteed to produce
signal drivers as returned representatives.

A `DriverMap` can also optionally preserve connections via intermediate
wires (e.g. querying the driver of a cell input port will return a
connected intermediate wire, querying the driver of that wire will
return the cell output port that's driving the wire).
 2024-08-21 11:00:21 +01:00