Clifford Wolf
3b796c033c
Add RTLIL::Const::ext[su](), fix RTLIL::SigSpec::extend_u0 for 0-size signals
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-23 14:38:48 +01:00
Clifford Wolf
370db33a4c
Add fmcombine pass
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-15 20:46:17 +01:00
Clifford Wolf
76c9c350e7
Add hashlib "<container>::element(int n)" methods
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-14 22:04:42 +01:00
Clifford Wolf
1cd04a6838
Fix a bug in handling quotes in multi-cmd lines in Yosys scripts
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-12 21:15:11 +01:00
Clifford Wolf
20c6a8c9b0
Improve determinism of IdString DB for similar scripts
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-11 20:12:28 +01:00
Clifford Wolf
d9bb5f3637
Add ENABLE_GLOB Makefile switch
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-11 01:08:36 -07:00
Clifford Wolf
c521f4632f
Merge pull request #819 from YosysHQ/clifford/optd
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Rename "yosys -D" to "yosys -U", add "yosys -D" with expected behavior
2019-02-22 06:55:48 +01:00
Clifford Wolf
0a6588569b
Rename "yosys -U" to "yosys -P" to avoid confusion about "undefine"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-21 15:51:59 +01:00
Clifford Wolf
953e0bf88d
Rename "yosys -D" to "yosys -U", add "yosys -D" with expected behavior
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-21 14:27:46 +01:00
Clifford Wolf
246391200e
Add FF support to wreduce
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-20 16:36:42 +01:00
Clifford Wolf
e70ebe557c
Add optional nullstr argument to log_id()
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-01-15 11:06:48 +01:00
whitequark
efa278e232
Fix typographical and grammatical errors and inconsistencies.
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The initial list of hits was generated with the codespell command
below, and each hit was evaluated and fixed manually while taking
context into consideration.
DIRS="kernel/ frontends/ backends/ passes/ techlibs/"
DIRS="${DIRS} libs/ezsat/ libs/subcircuit"
codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint
More hits were found by looking through comments and strings manually.
2019-01-02 13:12:17 +00:00
whitequark
18291c20d2
proc_clean: remove any empty cases if all cases use all-def compare.
2018-12-23 09:04:30 +00:00
whitequark
2ca237e086
tcl: add support for passing arguments to scripts.
2018-12-20 07:32:24 +00:00
Clifford Wolf
e90195b737
Improve ConstEval error handling for non-eval cell types
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-11-29 05:07:40 +01:00
Jon Burgess
6732e56632
Avoid assert when label is an empty string
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Calling back() on an empty string is not allowed and triggers
an assert with recent gcc:
$ cd manual/PRESENTATION_Intro
$ ../../yosys counter.ys
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/usr/include/c++/8/bits/basic_string.h:1136: std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::reference std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::back() [with _CharT = char; _Traits = std::char_traits<char>; _Alloc = std::allocator<char>; std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::reference = char&]: Assertion '!empty()' failed.
802 if (label.back() == ':' && GetSize(label) > 1)
(gdb) p label
$1 = ""
2018-10-28 14:57:04 +00:00
whentze
9ed77f5ba8
fix unhandled std::out_of_range when calling yosys with 3-character argument
2018-10-22 19:40:22 +02:00
Ruben Undheim
c50afc4246
Documentation improvements etc.
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- Mention new feature in the SystemVerilog section in the README file
- Commented changes much better
- Rename a few signals to make it clearer
- Prevent warning for unused signals in an easier way
- Add myself as copyright holder to 2 files
- Fix one potential memory leak (delete 'wire' if not in modport)
2018-10-13 20:34:44 +02:00
Ruben Undheim
458a94059e
Support for 'modports' for System Verilog interfaces
2018-10-12 21:11:48 +02:00
Ruben Undheim
75009ada3c
Synthesis support for SystemVerilog interfaces
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This time doing the changes mostly in AST before RTLIL generation
2018-10-12 21:11:36 +02:00
Adrian Wheeldon
1355492c89
Fix IdString M in setup_stdcells()
2018-10-04 15:36:26 +01:00
Miodrag Milanovic
c5e9034834
Fix Cygwin build and document needed packages
2018-09-19 10:16:53 +02:00
Clifford Wolf
67b1026297
Merge pull request #591 from hzeller/virtual-override
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Consistent use of 'override' for virtual methods in derived classes.
2018-08-15 14:05:38 +02:00
litghost
80d7e007ff
Map .eblif extension as blif.
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Signed-off-by: litghost <537074+litghost@users.noreply.github.com>
2018-08-13 14:02:53 -07:00
Henner Zeller
3aa4484a3c
Consistent use of 'override' for virtual methods in derived classes.
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o Not all derived methods were marked 'override', but it is a great
feature of C++11 that we should make use of.
o While at it: touched header files got a -*- c++ -*- for emacs to
provide support for that language.
o use YS_OVERRIDE for all override keywords (though we should probably
use the plain keyword going forward now that C++11 is established)
2018-07-20 23:51:06 -07:00
Henner Zeller
1a60126a34
Provide source-location logging.
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o Provide log_file_warning() and log_file_error() that prefix the log
message with <filename>:<lineno>: to be easily picked up by IDEs that
need to step through errors.
o Simplify some duplicate logging code in kernel/log.cc
o Use the new log functions in genrtlil.
2018-07-19 10:22:02 -07:00
Robert Ou
0abe7c6c77
Modify emscripten main to mount nodefs and to run arg as a script
2018-05-18 22:53:52 -07:00
Robert Ou
bd87462b47
Fix reading techlibs under emscripten
2018-05-18 22:42:33 -07:00
Christian Krämer
c1ecb1b2f1
Add "#ifdef __FreeBSD__"
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(Re-commit e3575a8
with corrected author field)
2018-05-13 13:08:26 +02:00
Clifford Wolf
1167538d26
Revert "Add "#ifdef __FreeBSD__""
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This reverts commit e3575a86c5
.
2018-05-13 13:06:36 +02:00
Johnny Sorocil
e3575a86c5
Add "#ifdef __FreeBSD__"
2018-05-05 13:02:44 +02:00
Clifford Wolf
5c03aeac60
Add "yosys -e regex" for turning warnings into errors
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-05-04 15:27:28 +02:00
Clifford Wolf
0acea3548b
Set stack size to at least 128 MB (large stack needed for parsing huge expressions)
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-03-27 15:04:10 +02:00
Edmond Cote
64ea55056a
Rename rename to renames
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Create TCL alias for rename command. Using renames. Following the same convention as proc -> procs.
2018-03-20 15:50:50 -07:00
Larry Doolittle
82fecc98c0
Harmonize uses of _WIN32 macro
2018-03-11 16:01:30 +01:00
Clifford Wolf
e5534a080e
Improve handling of warning messages
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-03-04 22:35:59 +01:00
Clifford Wolf
2935e8ea41
Update copyright header
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-03-04 21:31:10 +01:00
Clifford Wolf
eb67a7532b
Add $allconst and $allseq cell types
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-02-23 13:14:47 +01:00
Clifford Wolf
82c436587c
Do not create deep backtraces unless in ENABLE_DEBUG mode
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-02-03 15:04:39 +01:00
Clifford Wolf
a96c775a73
Add support for "yosys -E"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-01-07 16:36:13 +01:00
Clifford Wolf
c80315cea4
Bugfix in hierarchy handling of blackbox module ports
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-01-05 13:28:45 +01:00
Clifford Wolf
76afff7ef6
Add RTLIL::Const::is_fully_ones()
2017-12-14 02:06:39 +01:00
Clifford Wolf
96ad688849
Add SigSpec::is_fully_ones()
2017-12-14 01:29:09 +01:00
Kevin Kiningham
7350f7692a
Use quote includes for yosys.h
2017-12-13 13:27:52 -08:00
Clifford Wolf
9ae25039fb
Add support for editline as replacement for readline
2017-11-08 02:55:00 +01:00
Clifford Wolf
13eb47c692
Add src arguments to all cell creator helper functions
2017-09-09 10:16:48 +02:00
Clifford Wolf
8a66bd30c6
Update more stuff to use get_src_attribute() and set_src_attribute()
2017-09-01 12:26:55 +02:00
Jason Lowdermilk
71d43cfc08
Merge remote-tracking branch 'upstream/master'
2017-08-30 11:47:06 -06:00
Jason Lowdermilk
271e8ba7cd
fix indent level
2017-08-30 11:46:41 -06:00
Clifford Wolf
8530333439
Add {get,set}_src_attribute() methods on RTLIL::AttrObject
2017-08-30 11:39:11 +02:00