7 Commits

Author	SHA1	Message	Date
Clifford Wolf	765f172211	Changes to "memory" pass for new $memwr/$mem WR_EN interface	2014-07-16 12:49:50 +02:00
Clifford Wolf	a6750b3753	Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)	2014-02-03 13:01:45 +01:00
Clifford Wolf	67b0ce2578	Only generate write-enable $and if WE is not constant 1 in memory_map	2014-02-02 21:27:26 +01:00
Clifford Wolf	93a70959f3	Replaced RTLIL::Const::str with generic decoder method	2013-12-04 14:14:05 +01:00
Clifford Wolf	95dbacefbf	Fixed bug in synthesis of memories that are never written	2013-10-17 21:00:37 +02:00
Clifford Wolf	f3a849512f	Added help messages to memory_* passes	2013-03-01 10:17:35 +01:00
Clifford Wolf	7764d0ba1d	initial import	2013-01-05 11:13:26 +01:00