18 Commits

Author	SHA1	Message	Date
Eddie Hung	74ea438136	Add testcase for signal used as part input part output	2019-11-22 16:52:55 -08:00
Eddie Hung	c761fa49b7	Missing endmodule	2019-11-22 12:37:57 -08:00
Eddie Hung	5a30e3ac3b	Merge branch 'eddie/xaig_dff_adff' into xaig_dff	2019-11-21 16:15:25 -08:00
Eddie Hung	911a152b39	Add test	2019-11-21 16:13:28 -08:00
Eddie Hung	cd9e830b67	Add multi clock test	2019-11-20 13:28:55 -08:00
Eddie Hung	90c5ca330c	Add two tests	2019-11-19 16:57:58 -08:00
Eddie Hung	014606affe	Fix issue with part of PI being 1'bx	2019-06-20 17:38:16 -07:00
Eddie Hung	2e7b3eee40	Add a couple more tests	2019-06-12 15:43:43 -07:00
Eddie Hung	25befbf542	Rename to #23	2019-05-29 15:26:33 -07:00
Eddie Hung	aa2380c17a	Add abc_test024	2019-05-29 15:24:38 -07:00
Eddie Hung	92197326b8	Add abc9_test022	2019-05-28 12:43:07 -07:00
Eddie Hung	eec314e262	Remove topo sort no-loop assertion, with test	2019-04-24 21:06:53 -07:00
Eddie Hung	bfd71e0990	Fix abc9 with (* keep *) wires	2019-04-23 16:11:14 -07:00
Eddie Hung	dfb23a79dd	Uncomment out more tests	2019-02-26 12:18:48 -08:00
Eddie Hung	66b5f5166b	Enable two inout tests	2019-02-26 11:39:17 -08:00
Eddie Hung	65c8ccf7b5	Add broken testcases	2019-02-25 15:06:23 -08:00
Eddie Hung	c6fd057eda	Add abc9.v testcase to simple_abc9	2019-02-21 10:37:45 -08:00
Eddie Hung	43d5471570	Move tests/techmap/abc9 to simple_abc9	2019-02-20 15:34:59 -08:00