17 Commits

Author	SHA1	Message	Date
Miodrag Milanovic	1ecf6aee9b	Test fixes for latest iverilog	2022-09-21 15:46:43 +02:00
Clifford Wolf	450f6f59b4	Fixed bug with memories that do not have a down-to-zero data width	2016-08-22 14:27:46 +02:00
Clifford Wolf	9a101dc1f7	Fixed mem assignment in left-hand-side concatenation	2016-07-08 14:31:06 +02:00
Clifford Wolf	1761d08dd2	Bugfix and improvements in memory_share	2016-04-21 14:22:58 +02:00
Clifford Wolf	ddf3e2dc65	Bugfix in memory_dff	2015-10-31 22:01:41 +01:00
Clifford Wolf	e9368a1d7e	Various fixes for memories with offsets	2015-02-14 14:21:15 +01:00
Clifford Wolf	dcf2e24240	Added $meminit support to "memory" command	2015-02-14 12:55:03 +01:00
Clifford Wolf	913c304fe6	Added $meminit test case	2015-02-14 11:26:20 +01:00
Clifford Wolf	cad98bcd89	Added multi-dim memory test (requires iverilog git head)	2014-08-12 10:37:47 +02:00
Clifford Wolf	50f22ff30c	Renamed some of the test cases in tests/simple to avoid name collisions	2014-07-25 13:01:45 +02:00
Clifford Wolf	9b183539af	Implemented dynamic bit-/part-select for memory writes	2014-07-17 16:49:23 +02:00
Clifford Wolf	5867f6bcdc	Added support for bit/part select to mem2reg rewriter	2014-07-17 13:49:32 +02:00
Clifford Wolf	6d69d4aaa8	Added support for constant bit- or part-select for memory writes	2014-07-17 13:13:21 +02:00
Clifford Wolf	a6750b3753	Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)	2014-02-03 13:01:45 +01:00
Clifford Wolf	fb2bf934dc	Added correct handling of $memwr priority	2014-01-03 00:22:17 +01:00
Clifford Wolf	19dba2561e	Implemented part/bit select on memory read	2013-11-20 10:51:32 +01:00
Clifford Wolf	7764d0ba1d	initial import	2013-01-05 11:13:26 +01:00