riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
14,569 Commits 114 Branches 50 Tags 54 MiB
Commit Graph

5 Commits

Author SHA1 Message Date
Krystine Sherwin ee73a91f44
Remove references to ilang 2024-11-05 12:36:31 +13:00
Emil J. Tywoniak 01fd72520f proc_rom: test src attribute on memories 2024-07-29 10:13:45 +02:00
Amelia Cuss bf4a46ccb3 proc_rom: don't assert on big actionless switch. 
See the test case.  PROC_ROM will consider this for evaluation, even
though -- without any actions -- lhs is empty (but still "uniform").
A zero-width memory is constructed, which later fails check with:

ERROR: Assert `width != 0' failed in kernel/mem.cc:518.

Ensure we don't proceed if there's nothing to encode.
 2024-02-18 01:33:28 +11:00
Marcelina Kościelnicka 9450f308f0 proc_rom: Add special handling of const-0 address bits. 2022-05-18 17:32:30 +02:00
Marcelina Kościelnicka 990c9b8e11 Add proc_rom pass. 2022-05-13 00:37:14 +02:00