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11030 Commits

Author SHA1 Message Date
Miodrag Milanovic 44705102b5 Better error for unsupported SVA sequence 2020-09-18 17:08:00 +02:00
Yosys Bot 7affef7c17 Bump version 2020-09-18 00:10:08 +00:00
clairexen f176bd7778
Merge pull request #2329 from antmicro/arrays-fix-multirange-size 
Rewrite multirange arrays sizes [n] as [n-1:0]
 2020-09-17 18:27:05 +02:00
clairexen 9e937961dc
Merge pull request #2330 from antmicro/arrays-fix-multirange-access 
Fix unsupported subarray access detection
 2020-09-17 18:21:53 +02:00
Udi Finkelstein 7ed0e23e19 We can now handle array slices (e.g. $size(x[1]) etc. ) 2020-09-17 00:55:17 +03:00
Udi Finkelstein 6de7ba02e3 Fixed comments, removed debug message 2020-09-16 10:57:06 +03:00
Udi Finkelstein b548722bee Added $high(), $low(), $left(), $right() 2020-09-15 20:49:52 +03:00
N. Engelhardt 3238190797 use the new isPublic() in a few places 2020-09-14 12:43:18 +02:00
Yosys Bot 859e52af59 Bump version 2020-09-11 00:10:06 +00:00
Miodrag Milanović da3002e580
Merge pull request #2369 from Xiretza/gitignores 
Add missing gitignores for test artifacts
 2020-09-10 13:37:49 +02:00
Yosys Bot 474cd02eb5 Bump version 2020-09-04 00:10:06 +00:00
N. Engelhardt 4af04be0b7 add IdString::isPublic() 2020-09-03 17:37:58 +02:00
whitequark c66d1dfad1
Merge pull request #2371 from whitequark/cxxrtl-debug-info 
cxxrtl: expose port direction and driver kind in debug information
 2020-09-03 09:45:40 +00:00
Yosys Bot d963bdb484 Bump version 2020-09-03 00:10:06 +00:00
whitequark 691418e13a cxxrtl: expose driver kind in debug information. 
This can be useful to determine whether the wire should be a part of
a design checkpoint, whether it can be used to override design state,
and whether driving it may cause a conflict.
 2020-09-02 18:00:12 +00:00
whitequark c7b2f07edf cxxrtl: improve handling of FFs with async inputs (other than CLK). 
Before this commit, the meaning of "sync def" included some flip-flop
cells but not others. There was no actual reason for this; it was
just poorly defined.

After this commit, a "sync def" means that a wire holds design state
because it is connected directly to a flip-flop output, and may never
be unbuffered. This is not affected by presence of async inputs.
 2020-09-02 18:00:12 +00:00
whitequark b025ee0aa6 cxxrtl: expose port direction in debug information. 
This can be useful to distinguish e.g. a combinatorially driven wire
with type `CXXRTL_VALUE` from a module input with the same type, as
well as general introspection.
 2020-09-02 17:19:11 +00:00
whitequark 8d6e5c6391 cxxrtl: fix typo in comment. NFC. 2020-09-02 15:23:49 +00:00
whitequark d880f6eda2 cxxrtl: fix inaccuracy in CXXRTL_ALIAS documentation. NFC. 
Nodes driven by a constant value have type CXXRTL_VALUE and their
`next` pointer set to NULL. (This is already documented.)
 2020-09-02 15:23:47 +00:00
Miodrag Milanovic 3f27a4ea68 Use latest verific 2020-09-02 10:22:25 +02:00
Yosys Bot 463869bf4f Bump version 2020-09-02 00:10:07 +00:00
clairexen a10893072b
Merge pull request #2352 from zachjs/const-func-localparam 
Allow localparams in constant functions
 2020-09-01 17:31:48 +02:00
clairexen c1a6097376
Merge pull request #2366 from zachjs/library-format 
Simple support for %l format specifier
 2020-09-01 17:30:36 +02:00
clairexen 3e1840d036
Merge pull request #2353 from zachjs/top-scope 
Module name scope support
 2020-09-01 17:30:09 +02:00
clairexen 452442ac2f
Merge pull request #2365 from zachjs/const-arg-loop-split-type 
Fix constant args used with function ports split across declarations
 2020-09-01 17:28:35 +02:00
Yosys Bot 244af8b8b7 Bump version 2020-09-01 00:10:06 +00:00
Xiretza 6224fd9055
Add missing gitignores for test artifacts 2020-08-31 19:43:51 +02:00
Miodrag Milanovic 04d5692a85 Reorder to prevent crash 2020-08-31 12:22:26 +02:00
clairexen d23e4b4dce
Merge pull request #2368 from YosysHQ/verific_portrange 
Fix import of VHDL enums
 2020-08-31 11:58:29 +02:00
Miodrag Milanovic 3af499c60f ast recognize lower case x and z and verific gives upper case 2020-08-30 13:33:03 +02:00
Miodrag Milanovic 2f93579bd1 Do not check for 1 and 0 only 2020-08-30 13:15:06 +02:00
Miodrag Milanovic b1e3bc059c Fix import of VHDL enums 2020-08-30 12:25:23 +02:00
Yosys Bot 3030c2b46c Bump version 2020-08-30 00:10:07 +00:00
whitequark c1fff52477
write_smt2: fix SMT-LIB tutorial URL 2020-08-29 20:02:35 +00:00
Zachary Snow c7ceed3fd3 Simple support for %l format specifier 
Yosys doesn't support libraries, so this provides the same behavior as
%m, as some other tools have opted to do.
 2020-08-29 13:33:31 -04:00
Zachary Snow ecc5c23b4d Fix constant args used with function ports split across declarations 2020-08-29 13:31:02 -04:00
Yosys Bot f752023556 Bump version 2020-08-29 00:10:06 +00:00
Dan Ravensloft 028f96e536 intel_alm: better map wide but shallow multiplies 2020-08-28 23:44:16 +02:00
Yosys Bot c75d8c7439 Bump version 2020-08-28 00:10:07 +00:00
Miodrag Milanović cc0a4e8f39
Merge pull request #2364 from whitequark/manual-typo 
manual: fix typo
 2020-08-27 18:35:53 +02:00
whitequark eae88df016 manual: fix typo. 2020-08-27 16:34:48 +00:00
whitequark a0177569ac
Merge pull request #2357 from whitequark/cxxflags-MP 
Add -MP to CXXFLAGS
 2020-08-27 11:40:57 +00:00
whitequark 2d10d59d93
Merge pull request #2356 from whitequark/flatten-techmap-no-tpl_driven-sigmap 
flatten, techmap: don't canonicalize tpl driven bits via sigmap
 2020-08-27 11:28:31 +00:00
whitequark 702f7c0253
Merge pull request #2358 from whitequark/rename-ilang-to-rtlil 
Replace "ILANG" with "RTLIL" everywhere
 2020-08-27 11:24:06 +00:00
Marcelina Kościelnicka 880df4c897 dfflegalize: Fix decision tree for adffe. 
When an adffe is being legalized, and is not natively supported,
prioritize unmapping to adff over converting to dffsre if dffsre is not
natively supported itself.

Fixes #2361.
 2020-08-27 13:17:42 +02:00
Yosys Bot 925c0f2594 Bump version 2020-08-27 00:10:06 +00:00
Dan Ravensloft 1a07b330f8 intel_alm: Add multiply signedness to cells 
Quartus assumes unsigned multiplication by default, breaking signed
multiplies, so add an input signedness parameter to the MISTRAL_MUL*
cells to propagate to Quartus' <family>_mac cells.
 2020-08-26 22:50:16 +02:00
whitequark 00e7dec7f5 Replace "ILANG" with "RTLIL" everywhere. 
The only difference between "RTLIL" and "ILANG" is that the latter is
the text representation of the former, as opposed to the in-memory
graph representation. This distinction serves no purpose but confuses
people: it is not obvious that the ILANG backend writes RTLIL graphs.

Passes `write_ilang` and `read_ilang` are provided as aliases to
`write_rtlil` and `read_rtlil` for compatibility.
 2020-08-26 17:29:32 +00:00
whitequark deb19e1574 Add -MP to CXXFLAGS. 
This avoids an issue where deleting or moving headers breaks the next
incremental build until the outdated *.d files are deleted.
 2020-08-26 16:56:10 +00:00
whitequark 9f0892159e flatten, techmap: don't canonicalize tpl driven bits via sigmap. 
For connection `assign a = b;`, `sigmap(a)` returns `b`. This is
exactly the opposite of the desired canonicalization for driven bits.
Consider the following code:

    module foo(inout a, b);
      assign a = b;
    endmodule
    module bar(output c);
      foo f(c, 1'b0);
    endmodule

Before this commit, the inout ports would be swapped after flattening
(and cause a crash while attempting to drive a constant value).

This issue was introduced in 9f772eb9.

Fixes #2183.
 2020-08-26 16:29:42 +00:00