8 Commits

Author	SHA1	Message	Date
Clifford Wolf	dbfd8460a9	Allow $size and $bits in verilog mode, actually check test case	2017-09-29 11:56:43 +02:00
Clifford Wolf	8836943693	Added yet another resource sharing test case	2014-07-20 21:15:01 +02:00
Clifford Wolf	3b52121d32	now ignore init attributes on non-register wires in sat command	2014-07-05 11:18:38 +02:00
Clifford Wolf	482d9208aa	Added read_verilog -sv options, added support for bit, logic, ... allways_ff, always_comb, and always_latch	2014-06-12 11:54:20 +02:00
Clifford Wolf	039bb456cc	Added test cases for expose -evert-dff	2014-02-08 21:31:56 +01:00
Clifford Wolf	244e8ce1f4	Added splice command	2014-02-07 20:30:56 +01:00
Clifford Wolf	849fd62cfe	Added counters sat test case	2014-02-06 01:00:56 +01:00
Clifford Wolf	7a66b38c3e	Added test cases for sat command	2014-02-04 13:43:34 +01:00