66 Commits

Author	SHA1	Message	Date
Clifford Wolf	361e0d62ff	Replaced depricated NEW_WIRE macro with module->addWire() calls	2014-07-21 12:42:02 +02:00
Clifford Wolf	1c85584fe5	Do not create $dffsr cells with no-op resets in proc_dff	2014-06-19 12:29:29 +02:00
Clifford Wolf	8b508dc90b	Added workaround for vhdl-style edge triggers from vhdl2verilog to proc_arst	2014-02-21 23:34:45 +01:00
Clifford Wolf	8a8d444648	Tiny cleanup in proc_mux.cc	2014-01-03 16:54:59 +01:00
Clifford Wolf	369bf81a70	Added support for non-const === and !== (for miter circuits)	2013-12-27 14:20:15 +01:00
Clifford Wolf	09471846c5	Major improvements in mem2reg and added "init" sync rules	2013-11-21 13:49:00 +01:00
Clifford Wolf	64a5f8f75e	Added "proc_arst -global_arst" feature	2013-11-20 21:00:43 +01:00
Clifford Wolf	628b994cf6	Added support for complex set-reset flip-flops in proc_dff	2013-10-24 16:54:05 +02:00
Clifford Wolf	e679a5d046	Fixed handling of boolean attributes (passes)	2013-10-24 11:37:54 +02:00
Clifford Wolf	d61699843f	Improved handling of dff with async resets	2013-10-21 14:51:58 +02:00
Clifford Wolf	56ea230676	Added handling of multiple async paths in proc_arst	2013-10-19 00:50:13 +02:00
Clifford Wolf	bfa1a65fa9	Added dffsr support to proc_dff pass	2013-10-18 13:26:52 +02:00
Clifford Wolf	227520f94d	Added nosync attribute and some async reset related fixes	2013-03-25 17:13:14 +01:00
Johann Glaser	cd8008bda0	fixed typos	2013-03-18 07:28:31 +01:00
Clifford Wolf	f952309c81	Added help messages to proc_* passes	2013-03-01 09:26:29 +01:00
Clifford Wolf	7764d0ba1d	initial import	2013-01-05 11:13:26 +01:00