785bd44da7
rtlil: represent Const strings as std::string
2024-10-14 06:28:12 +02:00
4d469f461b
Add coarse-grain $buf buffer cell type
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Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2024-09-17 10:46:20 +02:00
7b47f645d7
Address warnings
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- Setting default values
- Fixing mismatched types
- Guarding unused var
2024-08-16 04:30:31 +12:00
f728927307
Add builtin celltype $scopeinfo
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Only declares the cell interface, doesn't make anything use or
understand $scopeinfo yet.
2024-02-06 17:51:24 +01:00
7203ba7bc1
Add bitwise `$bweqx` and `$bwmux` cells
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The new bitwise case equality (`$bweqx`) and bitwise mux (`$bwmux`)
cells enable compact encoding and decoding of 3-valued logic signals
using multiple 2-valued signals.
2022-11-30 18:24:35 +01:00
b982ab4f59
satgen, simlib: Consistent x-propagation for `$pmux` cells
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This updates satgen and simlib to use a `$pmux` model where the output
is fully X when the S input is not all zero or one-hot with no x bits.
2022-11-30 18:24:35 +01:00
ed0e14820e
sat: Add -set-def-formal option to force defined $any* outputs
2022-11-28 14:50:52 +01:00
c0063288d6
Add the $anyinit cell and the formalff pass
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These can be used to protect undefined flip-flop initialization values
from optimizations that are not sound for formal verification and can
help mapping all solver-provided values in witness traces for flows that
use different backends simultaneously.
2022-08-16 13:37:30 +02:00
93508d58da
Add $bmux and $demux cells.
2022-01-28 23:34:41 +01:00
63b9df8693
kernel/ff: Refactor FfData to enable FFs with async load.
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- *_en is split into *_ce (clock enable) and *_aload (async load aka
latch gate enable), so both can be present at once
- has_d is removed
- has_gclk is added (to have a clear marker for $ff)
- d_is_const and val_d leftovers are removed
- async2sync, clk2fflogic, opt_dff are updated to operate correctly on
FFs with async load
2021-10-02 20:19:48 +02:00
72787f52fc
Fixing old e-mail addresses and deadnames
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s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi;
s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi;
s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi;
s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi;
s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g ;
2021-06-08 00:39:36 +02:00
928fd40c2e
Respect \A_SIGNED for $shift
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This reflects the behaviour of $shr/$shl, which sign-extend their A
operands to the size of their output, then do a logical shift (shift in
0-bits).
2020-08-18 19:36:24 +02:00
0c6d0d4b5d
satgen: Add support for dffe, sdff, sdffe, sdffce cells.
2020-07-24 03:19:21 +02:00
85a1bb17ed
satgen: Move importCell out of the header.
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This function has no hope of ever getting inlined anyway, and it speeds
up yosys compile time by 7%.
2020-07-19 00:17:02 +02:00
Emil J. Tywoniak
Claire Xenia Wolf
Krystine Sherwin
Jannis Harder
Marcelina Kościelnicka
Xiretza