mirror of https://github.com/YosysHQ/yosys.git
Start unification effort for machxo2 and ecp5
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@ -1,6 +1,7 @@
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OBJS += techlibs/machxo2/synth_machxo2.o
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$(eval $(call add_share_file,share/machxo2,techlibs/ecp5/cells_io.vh))
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$(eval $(call add_share_file,share/machxo2,techlibs/machxo2/cells_map.v))
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$(eval $(call add_share_file,share/machxo2,techlibs/machxo2/cells_sim.v))
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@ -25,10 +25,6 @@ module \$lut (A, Y);
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endmodule
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// DFFs
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module \$_DFF_P_ (input D, C, output Q); FACADE_FF #(.CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(1'b0), .DI(D), .Q(Q)); endmodule
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module \$_DFF_P_ (input D, C, output Q); TRELLIS_FF #(.CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(1'b0), .DI(D), .Q(Q)); endmodule
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// IO- "$__" cells for the iopadmap pass.
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module \$__FACADE_OUTPAD (input I, output O); FACADE_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.PAD(O), .I(I), .T(1'b0)); endmodule
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module \$__FACADE_INPAD (input I, output O); FACADE_IO #(.DIR("INPUT")) _TECHMAP_REPLACE_ (.PAD(I), .O(O)); endmodule
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module \$__FACADE_TOUTPAD (input I, T, output O); FACADE_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.PAD(O), .I(I), .T(T)); endmodule
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module \$__FACADE_TINOUTPAD (input I, T, output O, inout B); FACADE_IO #(.DIR("BIDIR")) _TECHMAP_REPLACE_ (.PAD(B), .I(I), .O(O), .T(T)); endmodule
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`include "cells_io.vh"
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@ -11,7 +11,7 @@ module LUT4 #(
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assign Z = A ? s1[1] : s1[0];
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endmodule
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module FACADE_FF #(
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module TRELLIS_FF #(
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parameter GSR = "ENABLED",
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parameter CEMUX = "1",
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parameter CLKMUX = "0",
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@ -77,7 +77,7 @@ endmodule
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/* For consistency, input order matches TRELLIS_SLICE even though the BELs in
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prjtrellis were filled in clockwise order from bottom left. */
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module FACADE_SLICE #(
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module TRELLIS_SLICE #(
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parameter MODE = "LOGIC",
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parameter GSR = "ENABLED",
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parameter SRMODE = "LSR_OVER_CE",
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@ -139,33 +139,34 @@ module FACADE_SLICE #(
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endgenerate
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/* Reg can be fed either by M, or DI inputs; DI inputs muxes OFX and F
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outputs (in other words, feeds back into FACADE_SLICE). */
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outputs (in other words, feeds back into TRELLIS_SLICE). */
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wire di0 = (REG0_SD == "1") ? DI0 : M0;
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wire di1 = (REG1_SD == "1") ? DI1 : M1;
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FACADE_FF#(.GSR(GSR), .CEMUX(CEMUX), .CLKMUX(CLKMUX), .LSRMUX(LSRMUX),
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TRELLIS_FF#(.GSR(GSR), .CEMUX(CEMUX), .CLKMUX(CLKMUX), .LSRMUX(LSRMUX),
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.LSRONMUX(LSRONMUX), .SRMODE(SRMODE), .REGSET(REG0_REGSET),
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.REGMODE(REGMODE)) REG_0 (.CLK(CLK), .DI(di0), .LSR(LSR), .CE(CE), .Q(Q0));
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FACADE_FF#(.GSR(GSR), .CEMUX(CEMUX), .CLKMUX(CLKMUX), .LSRMUX(LSRMUX),
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TRELLIS_FF#(.GSR(GSR), .CEMUX(CEMUX), .CLKMUX(CLKMUX), .LSRMUX(LSRMUX),
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.LSRONMUX(LSRONMUX), .SRMODE(SRMODE), .REGSET(REG1_REGSET),
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.REGMODE(REGMODE)) REG_1 (.CLK(CLK), .DI(di1), .LSR(LSR), .CE(CE), .Q(Q1));
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endmodule
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module FACADE_IO #(
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module TRELLIS_IO #(
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parameter DIR = "INPUT"
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) (
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inout PAD,
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(* iopad_external_pin *)
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inout B,
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input I, T,
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output O
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);
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generate
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if (DIR == "INPUT") begin
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assign O = PAD;
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assign O = B;
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end else if (DIR == "OUTPUT") begin
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assign PAD = T ? 1'bz : I;
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assign B = T ? 1'bz : I;
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end else if (DIR == "BIDIR") begin
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assign PAD = T ? 1'bz : I;
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assign O = PAD;
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assign B = T ? 1'bz : I;
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assign O = B;
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end else begin
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ERROR_UNKNOWN_IO_MODE error();
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end
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@ -320,14 +321,8 @@ module DP8KC(
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parameter INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
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endmodule
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// IO- "$__" cells for the iopadmap pass. These are temporary cells not meant
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// to be instantiated by the end user. They are required in this file for
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// attrmvcp to work.
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(* blackbox *)
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module \$__FACADE_OUTPAD (input I, output O); endmodule
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(* blackbox *)
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module \$__FACADE_INPAD (input I, output O); endmodule
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(* blackbox *)
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module \$__FACADE_TOUTPAD (input I, T, output O); endmodule
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(* blackbox *)
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module \$__FACADE_TINOUTPAD (input I, T, output O, inout B); endmodule
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`ifndef NO_INCLUDES
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`include "cells_io.vh"
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`endif
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@ -214,9 +214,9 @@ struct SynthMachXO2Pass : public ScriptPass
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{
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if (!noiopad || help_mode)
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{
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run("iopadmap -bits -outpad $__FACADE_OUTPAD I:O -inpad $__FACADE_INPAD O:I -toutpad $__FACADE_TOUTPAD ~T:I:O -tinoutpad $__FACADE_TINOUTPAD ~T:O:I:B A:top");
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run("attrmvcp -attr src -attr LOC t:$__FACADE_OUTPAD %x:+[O] t:$__FACADE_TOUTPAD %x:+[O] t:$__FACADE_TINOUTPAD %x:+[B]");
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run("attrmvcp -attr src -attr LOC -driven t:$__FACADE_INPAD %x:+[I]");
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run("iopadmap -bits -outpad OB I:O -inpad IB O:I -toutpad OBZ ~T:I:O -tinoutpad BB ~T:O:I:B A:top", "(only if '-iopad')");
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run("attrmvcp -attr src -attr LOC t:OB %x:+[O] t:OBZ %x:+[O] t:BB %x:+[B]");
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run("attrmvcp -attr src -attr LOC -driven t:IB %x:+[I]");
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}
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}
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