mirror of https://github.com/YosysHQ/yosys.git
Replace `std::map` with `dict`.
Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
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@ -49,9 +49,9 @@ struct ScatterPass : public Pass {
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for (auto module : design->selected_modules())
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for (auto module : design->selected_modules())
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{
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{
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for (auto cell : module->cells()) {
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for (auto cell : module->cells()) {
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std::map<RTLIL::IdString, std::pair<RTLIL::SigSpec, RTLIL::SigSpec>> new_connections;
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dict<RTLIL::IdString, RTLIL::SigSig> new_connections;
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for (auto conn : cell->connections())
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for (auto conn : cell->connections())
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new_connections.emplace(conn.first, std::make_pair(conn.second, module->addWire(NEW_ID, conn.second.size())));
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new_connections.emplace(conn.first, RTLIL::SigSig(conn.second, module->addWire(NEW_ID, GetSize(conn.second))));
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for (auto &it : new_connections) {
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for (auto &it : new_connections) {
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if (ct.cell_output(cell->type, it.first))
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if (ct.cell_output(cell->type, it.first))
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module->connect(RTLIL::SigSig(it.second.first, it.second.second));
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module->connect(RTLIL::SigSig(it.second.first, it.second.second));
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