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Added FF cells to xilinx/cells_sim.v

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Clifford Wolf 2015-01-16 14:59:40 +01:00
parent b197279f3c
commit fd8c8d4fd3
1 changed files with 111 additions and 111 deletions
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222
techlibs/xilinx/cells_sim.v
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@ -1,150 +1,150 @@
module IBUF(O, I); module VCC(output P);
output O; assign P = 1;
input I;
assign O = I;
endmodule endmodule
module OBUF(O, I); module GND(output G);
output O; assign G = 0;
input I;
assign O = I;
endmodule endmodule
module BUFGP(O, I); module IBUF(output O, input I);
output O; assign O = I;
input I;
assign O = I;
endmodule endmodule
module OBUFT(O, I, T); module OBUF(output O, input I);
output O; assign O = I;
input I, T;
assign O = T ? 1'bz : I;
endmodule endmodule
module GND(G); module BUFGP(output O, input I);
output G; assign O = I;
assign G = 0;
endmodule endmodule
module INV(O, I); module OBUFT(output O, input I, T);
input I; assign O = T ? 1'bz : I;
output O;
assign O = !I;
endmodule endmodule
module LUT1(O, I0); module INV(output O, input I);
parameter [1:0] INIT = 0; assign O = !I;
input I0;
output O;
assign O = I0 ? INIT[1] : INIT[0];
endmodule endmodule
module LUT2(O, I0, I1); module LUT1(output O, input I0);
parameter [3:0] INIT = 0; parameter [1:0] INIT = 0;
input I0, I1; assign O = I0 ? INIT[1] : INIT[0];
output O;
wire [ 1: 0] s1 = I1 ? INIT[ 3: 2] : INIT[ 1: 0];
assign O = I0 ? s1[1] : s1[0];
endmodule endmodule
module LUT3(O, I0, I1, I2); module LUT2(output O, input I0, I1);
parameter [7:0] INIT = 0; parameter [3:0] INIT = 0;
input I0, I1, I2; wire [ 1: 0] s1 = I1 ? INIT[ 3: 2] : INIT[ 1: 0];
output O; assign O = I0 ? s1[1] : s1[0];
wire [ 3: 0] s2 = I2 ? INIT[ 7: 4] : INIT[ 3: 0];
wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
assign O = I0 ? s1[1] : s1[0];
endmodule endmodule
module LUT4(O, I0, I1, I2, I3); module LUT3(output O, input I0, I1, I2);
parameter [15:0] INIT = 0; parameter [7:0] INIT = 0;
input I0, I1, I2, I3; wire [ 3: 0] s2 = I2 ? INIT[ 7: 4] : INIT[ 3: 0];
output O; wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
wire [ 7: 0] s3 = I3 ? INIT[15: 8] : INIT[ 7: 0]; assign O = I0 ? s1[1] : s1[0];
wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0];
wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
assign O = I0 ? s1[1] : s1[0];
endmodule endmodule
module LUT5(O, I0, I1, I2, I3, I4); module LUT4(output O, input I0, I1, I2, I3);
parameter [31:0] INIT = 0; parameter [15:0] INIT = 0;
input I0, I1, I2, I3, I4; wire [ 7: 0] s3 = I3 ? INIT[15: 8] : INIT[ 7: 0];
output O; wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0];
wire [15: 0] s4 = I4 ? INIT[31:16] : INIT[15: 0]; wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
wire [ 7: 0] s3 = I3 ? s4[15: 8] : s4[ 7: 0]; assign O = I0 ? s1[1] : s1[0];
wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0];
wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
assign O = I0 ? s1[1] : s1[0];
endmodule endmodule
module LUT6(O, I0, I1, I2, I3, I4, I5); module LUT5(output O, input I0, I1, I2, I3, I4);
parameter [63:0] INIT = 0; parameter [31:0] INIT = 0;
input I0, I1, I2, I3, I4, I5; wire [15: 0] s4 = I4 ? INIT[31:16] : INIT[15: 0];
output O; wire [ 7: 0] s3 = I3 ? s4[15: 8] : s4[ 7: 0];
wire [31: 0] s5 = I5 ? INIT[63:32] : INIT[31: 0]; wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0];
wire [15: 0] s4 = I4 ? s5[31:16] : s5[15: 0]; wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
wire [ 7: 0] s3 = I3 ? s4[15: 8] : s4[ 7: 0]; assign O = I0 ? s1[1] : s1[0];
wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0];
wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
assign O = I0 ? s1[1] : s1[0];
endmodule endmodule
module MUXCY(O, CI, DI, S); module LUT6(output O, input I0, I1, I2, I3, I4, I5);
input CI, DI, S; parameter [63:0] INIT = 0;
output O; wire [31: 0] s5 = I5 ? INIT[63:32] : INIT[31: 0];
assign O = S ? CI : DI; wire [15: 0] s4 = I4 ? s5[31:16] : s5[15: 0];
wire [ 7: 0] s3 = I3 ? s4[15: 8] : s4[ 7: 0];
wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0];
wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
assign O = I0 ? s1[1] : s1[0];
endmodule endmodule
module MUXF7(O, I0, I1, S); module MUXCY(output O, input CI, DI, S);
input I0, I1, S; assign O = S ? CI : DI;
output O;
assign O = S ? I1 : I0;
endmodule endmodule
module MUXF8(O, I0, I1, S); module MUXF7(output O, input I0, I1, S);
input I0, I1, S; assign O = S ? I1 : I0;
output O;
assign O = S ? I1 : I0;
endmodule endmodule
module VCC(P); module MUXF8(output O, input I0, I1, S);
output P; assign O = S ? I1 : I0;
assign P = 1;
endmodule endmodule
module XORCY(O, CI, LI); module XORCY(output O, input CI, LI);
input CI, LI; assign O = CI ^ LI;
output O;
assign O = CI ^ LI;
endmodule endmodule
module CARRY4(CO, O, CI, CYINIT, DI, S); module CARRY4(output [3:0] CO, O, input CI, CYINIT, input [3:0] DI, S);
output [3:0] CO, O; assign O = S ^ {CO[2:0], CI | CYINIT};
input CI, CYINIT; assign CO[0] = S[0] ? CI | CYINIT : DI[0];
input [3:0] DI, S; assign CO[1] = S[1] ? CO[0] : DI[1];
wire ci_or_cyinit; assign CO[2] = S[2] ? CO[1] : DI[2];
assign O = S ^ {CO[2:0], ci_or_cyinit}; assign CO[3] = S[3] ? CO[2] : DI[3];
assign CO[0] = S[0] ? ci_or_cyinit : DI[0];
assign CO[1] = S[1] ? CO[0] : DI[1];
assign CO[2] = S[2] ? CO[1] : DI[2];
assign CO[3] = S[3] ? CO[2] : DI[3];
assign ci_or_cyinit = CI | CYINIT;
endmodule endmodule
/* module FDRE (output reg Q, input C, CE, D, R);
module FDRE (Q, C, CR, D, R); parameter [0:0] INIT = 1'b0;
parameter [0:0] INIT = 1'b0, parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0, parameter [0:0] IS_D_INVERTED = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0, parameter [0:0] IS_R_INVERTED = 1'b0;
parameter [0:0] IS_R_INVERTED = 1'b0 initial Q <= INIT;
output Q; generate case (|IS_C_INVERTED)
input C; 1'b0: always @(posedge C) if (R == !IS_R_INVERTED) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
input CE; 1'b1: always @(negedge C) if (R == !IS_R_INVERTED) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
input D; endcase endgenerate
input R; endmodule
// -- FIXME --
module FDSE (output reg Q, input C, CE, D, S);
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0;
parameter [0:0] IS_S_INVERTED = 1'b0;
initial Q <= INIT;
generate case (|IS_C_INVERTED)
1'b0: always @(posedge C) if (S == !IS_S_INVERTED) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
1'b1: always @(negedge C) if (S == !IS_S_INVERTED) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
endcase endgenerate
endmodule
module FDCE (output reg Q, input C, CE, D, CLR);
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0;
parameter [0:0] IS_CLR_INVERTED = 1'b0;
initial Q <= INIT;
generate case ({|IS_C_INVERTED, |IS_CLR_INVERTED})
2'b00: always @(posedge C, posedge CLR) if ( CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
2'b01: always @(posedge C, negedge CLR) if (!CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
2'b10: always @(negedge C, posedge CLR) if ( CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
2'b11: always @(negedge C, negedge CLR) if (!CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
endcase endgenerate
endmodule
module FDPE (output reg Q, input C, CE, D, PRE);
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0;
parameter [0:0] IS_PRE_INVERTED = 1'b0;
initial Q <= INIT;
generate case ({|IS_C_INVERTED, |IS_PRE_INVERTED})
2'b00: always @(posedge C, posedge PRE) if ( PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
2'b01: always @(posedge C, negedge PRE) if (!PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
2'b10: always @(negedge C, posedge PRE) if ( PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
2'b11: always @(negedge C, negedge PRE) if (!PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
endcase endgenerate
endmodule endmodule
*/