mirror of https://github.com/YosysHQ/yosys.git
ice40: add support for both 1364.1 and LSE RAM/ROM attributes.
This commit tries to carefully follow the documented behavior of LSE
and Synplify. It will use `syn_ramstyle` attribute if there are any
write ports, and `syn_romstyle` attribute otherwise.
* LSE supports both `syn_ramstyle` and `syn_romstyle`.
* Synplify only supports `syn_ramstyle`, with same values as LSE.
* Synplify also supports `syn_rw_conflict_logic`, which is not
documented as supported for LSE.
Limitations of the Yosys implementation:
* LSE/Synplify appear to interpret attribute values insensitive
to case. There is currently no way to do this in Yosys (attrmap
can only change case of attribute names).
* LSE/Synplify support `syn_ramstyle="block_ram,no_rw_check"`
syntax to turn off insertion of transparency logic. There is
currently no way to support multiple valued attributes in
memory_bram. It is also not clear if that is a good idea, since
it can cause sim/synth mismatches.
* LSE/Synplify/1364.1 support block ROM inference from full case
statements. Yosys does not currently perform this transformation.
* LSE/Synplify propagate `syn_ramstyle`/`syn_romstyle` attributes
from the module to the inner memories. There is currently no way
to do this in Yosys (attrmvcp only works on cells and wires).
This commit is contained in:
whitequark
parent
29d130dee9
commit
fc28bf55aa
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@ -28,13 +28,72 @@ bram $__ICE40_RAM4K_M123
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clkpol 2 3
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endbram
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# The syn_* attributes are described in:
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# https://www.latticesemi.com/-/media/LatticeSemi/Documents/Tutorials/AK/LatticeDiamondTutorial311.ashx
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match $__ICE40_RAM4K_M0
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# implicitly requested RAM or ROM
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attribute !syn_ramstyle syn_ramstyle=auto
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attribute !syn_romstyle syn_romstyle=auto
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attribute !ram_block
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attribute !rom_block
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attribute !logic_block
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min efficiency 2
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make_transp
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or_next_if_better
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endmatch
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match $__ICE40_RAM4K_M0
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# explicitly requested RAM
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attribute syn_ramstyle=block_ram ram_block
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attribute !syn_romstyle
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attribute !rom_block
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attribute !logic_block
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min wports 1
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make_transp
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or_next_if_better
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endmatch
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match $__ICE40_RAM4K_M0
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# explicitly requested ROM
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attribute syn_romstyle=ebr rom_block
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attribute !syn_ramstyle
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attribute !ram_block
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attribute !logic_block
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max wports 0
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make_transp
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or_next_if_better
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endmatch
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match $__ICE40_RAM4K_M123
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# implicitly requested RAM or ROM
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attribute !syn_ramstyle syn_ramstyle=auto
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attribute !syn_romstyle syn_romstyle=auto
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attribute !ram_block
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attribute !rom_block
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attribute !logic_block
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min efficiency 2
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make_transp
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or_next_if_better
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endmatch
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match $__ICE40_RAM4K_M123
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min efficiency 2
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# explicitly requested RAM
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attribute syn_ramstyle=block_ram ram_block
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attribute !syn_romstyle
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attribute !rom_block
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attribute !logic_block
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min wports 1
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make_transp
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or_next_if_better
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endmatch
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match $__ICE40_RAM4K_M123
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# explicitly requested ROM
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attribute syn_romstyle=ebr rom_block
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attribute !syn_ramstyle
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attribute !ram_block
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attribute !logic_block
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max wports 0
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make_transp
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endmatch
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@ -18,6 +18,7 @@ module sync_ram_sp #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10)
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end
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assign data_out = data_out_r;
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endmodule // sync_ram_sp
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@ -41,5 +42,6 @@ module sync_ram_sdp #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10)
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end
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assign data_out = data_out_r;
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endmodule // sync_ram_sdp
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@ -0,0 +1,31 @@
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`default_nettype none
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module sync_rom #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10)
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(input wire clk,
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input wire [ADDRESS_WIDTH-1:0] address_in,
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output wire [DATA_WIDTH-1:0] data_out);
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localparam WORD = (DATA_WIDTH-1);
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localparam DEPTH = (2**ADDRESS_WIDTH-1);
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reg [WORD:0] data_out_r;
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reg [WORD:0] memory [0:DEPTH];
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integer i,j = 16'hACE1;
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initial
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for (i = 0; i <= DEPTH; i++) begin
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// In case this ROM will be implemented in fabric: fill the memory with some data
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// uncorrelated with the address, or Yosys might see through the ruse and e.g. not
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// emit any LUTs at all for `memory[i] = i;`, just a latch.
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memory[i] = j;
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j = j ^ (j >> 7);
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j = j ^ (j << 9);
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j = j ^ (j >> 13);
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end
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always @(posedge clk) begin
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data_out_r <= memory[address_in];
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end
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assign data_out = data_out_r;
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endmodule // sync_rom
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@ -0,0 +1,126 @@
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# RAM bits <= 4K; Data width <= 16; Address width <= 11: -> SB_RAM40_4K
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design -reset; read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 11 -set DATA_WIDTH 2 sync_ram_sdp
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synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 1 t:SB_RAM40_4K
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design -reset; read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 4 sync_ram_sdp
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synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 1 t:SB_RAM40_4K
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design -reset; read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 8 sync_ram_sdp
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synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 1 t:SB_RAM40_4K
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design -reset; read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 16 sync_ram_sdp
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synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 1 t:SB_RAM40_4K
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## With parameters
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design -reset; read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp
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synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 0 t:SB_RAM40_4K # too inefficient
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select -assert-min 1 t:SB_DFFE
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design -reset; read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp
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setattr -set syn_ramstyle "block_ram" m:memory
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synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 1 t:SB_RAM40_4K
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design -reset; read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp
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setattr -set ram_block 1 m:memory
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synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 1 t:SB_RAM40_4K
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design -reset; read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp
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setattr -set logic_block 1 m:memory
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synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 0 t:SB_RAM40_4K # requested FFRAM explicitly
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select -assert-min 1 t:SB_DFFE
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design -reset; read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp
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setattr -set syn_romstyle "ebr" m:memory
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synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 0 t:SB_RAM40_4K # requested BROM but this is a RAM
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select -assert-min 1 t:SB_DFFE
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design -reset; read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp
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setattr -set rom_block 1 m:memory
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synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 0 t:SB_RAM40_4K # requested BROM but this is a RAM
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select -assert-min 1 t:SB_DFFE
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# ROM bits <= 4K; Data width <= 16; Address width <= 11: -> SB_RAM40_4K
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design -reset; read_verilog ../common/blockrom.v
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chparam -set ADDRESS_WIDTH 11 -set DATA_WIDTH 2 sync_rom
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synth_ice40 -top sync_rom; cd sync_rom
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select -assert-count 1 t:SB_RAM40_4K
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design -reset; read_verilog ../common/blockrom.v
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chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 4 sync_rom
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synth_ice40 -top sync_rom; cd sync_rom
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select -assert-count 1 t:SB_RAM40_4K
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design -reset; read_verilog ../common/blockrom.v
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chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 8 sync_rom
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synth_ice40 -top sync_rom; cd sync_rom
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select -assert-count 1 t:SB_RAM40_4K
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design -reset; read_verilog ../common/blockrom.v
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chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 16 sync_rom
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synth_ice40 -top sync_rom; cd sync_rom
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select -assert-count 1 t:SB_RAM40_4K
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## With parameters
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design -reset; read_verilog ../common/blockrom.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom
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write_ilang
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synth_ice40 -top sync_rom; cd sync_rom
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select -assert-count 0 t:SB_RAM40_4K # too inefficient
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select -assert-min 1 t:SB_LUT4
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design -reset; read_verilog ../common/blockrom.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom
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setattr -set syn_romstyle "ebr" m:memory
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synth_ice40 -top sync_rom; cd sync_rom
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select -assert-count 1 t:SB_RAM40_4K
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design -reset; read_verilog ../common/blockrom.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom
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setattr -set rom_block 1 m:memory
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synth_ice40 -top sync_rom; cd sync_rom
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select -assert-count 1 t:SB_RAM40_4K
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design -reset; read_verilog ../common/blockrom.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom
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setattr -set logic_block 1 m:memory
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synth_ice40 -top sync_rom; cd sync_rom
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select -assert-count 0 t:SB_RAM40_4K # requested LUTROM explicitly
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select -assert-min 1 t:SB_LUT4
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design -reset; read_verilog ../common/blockrom.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom
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setattr -set syn_ramstyle "block_ram" m:memory
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synth_ice40 -top sync_rom; cd sync_rom
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select -assert-count 0 t:SB_RAM40_4K # requested BRAM but this is a ROM
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select -assert-min 1 t:SB_LUT4
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design -reset; read_verilog ../common/blockrom.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom
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setattr -set ram_block 1 m:memory
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synth_ice40 -top sync_rom; cd sync_rom
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select -assert-count 0 t:SB_RAM40_4K # requested BRAM but this is a ROM
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select -assert-min 1 t:SB_LUT4
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