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Merge remote-tracking branch 'origin/master' into xc7dsp

This commit is contained in:
Eddie Hung 2019-09-18 12:40:21 -07:00
parent 44bf4ac35c b66c99ece0
commit f7dbfef792
3 changed files with 44 additions and 15 deletions
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26
passes/pmgen/peepopt_dffmux.pmg
View File

@ -42,6 +42,12 @@ code
rst = port(rstmux, rstmuxBA).as_const(); rst = port(rstmux, rstmuxBA).as_const();
int width = GetSize(D); int width = GetSize(D);
SigSpec &ceA = cemux->connections_.at(\A);
SigSpec &ceB = cemux->connections_.at(\B);
SigSpec &ceY = cemux->connections_.at(\Y);
SigSpec &dffD = dff->connections_.at(\D);
SigSpec &dffQ = dff->connections_.at(\Q);
if (D[width-1] == D[width-2]) { if (D[width-1] == D[width-2]) {
did_something = true; did_something = true;
@ -61,12 +67,12 @@ code
} }
} }
cemux->connections_.at(\A).remove(i, width-i); ceA.remove(i, width-i);
cemux->connections_.at(\B).remove(i, width-i); ceB.remove(i, width-i);
cemux->connections_.at(\Y).remove(i, width-i); ceY.remove(i, width-i);
cemux->fixup_parameters(); cemux->fixup_parameters();
dff->connections_.at(\D).remove(i, width-i); dffD.remove(i, width-i);
dff->connections_.at(\Q).remove(i, width-i); dffQ.remove(i, width-i);
dff->fixup_parameters(); dff->fixup_parameters();
log("dffcemux pattern in %s: dff=%s, cemux=%s; removed top %d bits.\n", log_id(module), log_id(dff), log_id(cemux), width-i); log("dffcemux pattern in %s: dff=%s, cemux=%s; removed top %d bits.\n", log_id(module), log_id(dff), log_id(cemux), width-i);
@ -88,11 +94,11 @@ code
if (init == State::Sx || init == D[i].data) { if (init == State::Sx || init == D[i].data) {
count++; count++;
module->connect(Q[i], D[i]); module->connect(Q[i], D[i]);
cemux->connections_.at(\A).remove(i); ceA.remove(i);
cemux->connections_.at(\B).remove(i); ceB.remove(i);
cemux->connections_.at(\Y).remove(i); ceY.remove(i);
dff->connections_.at(\D).remove(i); dffD.remove(i);
dff->connections_.at(\Q).remove(i); dffQ.remove(i);
} }
} }
if (count > 0) { if (count > 0) {

1
passes/pmgen/peepopt_shiftmul.pmg
View File

@ -50,7 +50,6 @@ code
if (GetSize(const_factor_cnst) > 20) if (GetSize(const_factor_cnst) > 20)
reject; reject;
if (shift->type.in($shift, $shiftx))
if (GetSize(port(shift, \Y)) > const_factor) if (GetSize(port(shift, \Y)) > const_factor)
reject; reject;

28
tests/various/peepopt.ys
View File

@ -16,7 +16,7 @@ select -assert-count 0 t:$shiftx t:* %D
design -reset design -reset
read_verilog <<EOT read_verilog <<EOT
module peepopt_shiftmul_1 (output [7:0] y, input [2:0] w); module peepopt_shiftmul_1 (output [7:0] y, input [2:0] w);
assign y = 1'b1 >> (w * (8'b110)); assign y = 1'b1 >> (w * (3'b110));
endmodule endmodule
EOT EOT
@ -25,7 +25,31 @@ equiv_opt -assert peepopt
design -load postopt design -load postopt
clean clean
select -assert-count 1 t:$shr select -assert-count 1 t:$shr
select -assert-count 0 t:$mul select -assert-count 1 t:$mul
select -assert-count 0 t:$shr t:$mul %% t:* %D
####################
design -reset
read_verilog <<EOT
module peepopt_shiftmul_2 (input [11:0] D, input [1:0] S, output [11:0] Y);
assign Y = D >> (S*3);
endmodule
EOT
prep
design -save gold
peepopt
design -stash gate
design -import gold -as gold peepopt_shiftmul_2
design -import gate -as gate peepopt_shiftmul_2
miter -equiv -make_assert -make_outputs -ignore_gold_x -flatten gold gate miter
sat -show-public -enable_undef -prove-asserts miter
cd gate
select -assert-count 1 t:$shr
select -assert-count 1 t:$mul
select -assert-count 0 t:$shr t:$mul %% t:* %D select -assert-count 0 t:$shr t:$mul %% t:* %D
#################### ####################