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aiger2: Fix relative ordering of PI/POs and box I/Os

This commit is contained in:
Martin Povišer 2024-10-05 18:03:52 +02:00
parent 8d12492610
commit f7c7371ea9
1 changed files with 2 additions and 2 deletions
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4
backends/aiger2/aiger.cc
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@ -934,7 +934,7 @@ struct XAigerWriter : AigerWriter {
});
for (auto [cursor, box, def] : opaque_boxes)
append_box_ports(box, cursor, true);
append_box_ports(box, cursor, false);
holes_module = design->addModule(NEW_ID);
std::vector<RTLIL::Wire *> holes_pis;
@ -1024,7 +1024,7 @@ struct XAigerWriter : AigerWriter {
}
for (auto [cursor, box, def] : opaque_boxes)
append_box_ports(box, cursor, false);
append_box_ports(box, cursor, true);
write_be32(h_buffer, 1);
write_be32(h_buffer, pis.size());