From f7c7371ea9157ef1199c4a76d20364b3699313b4 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Martin=20Povi=C5=A1er?= <povik@cutebit.org>
Date: Sat, 5 Oct 2024 18:03:52 +0200
Subject: [PATCH] aiger2: Fix relative ordering of PI/POs and box I/Os

---
 backends/aiger2/aiger.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/backends/aiger2/aiger.cc b/backends/aiger2/aiger.cc
index 89ef06a37..9df9c9b20 100644
--- a/backends/aiger2/aiger.cc
+++ b/backends/aiger2/aiger.cc
@@ -934,7 +934,7 @@ struct XAigerWriter : AigerWriter {
 		});
 
 		for (auto [cursor, box, def] : opaque_boxes)
-			append_box_ports(box, cursor, true);
+			append_box_ports(box, cursor, false);
 
 		holes_module = design->addModule(NEW_ID);
 		std::vector<RTLIL::Wire *> holes_pis;
@@ -1024,7 +1024,7 @@ struct XAigerWriter : AigerWriter {
 		}
 
 		for (auto [cursor, box, def] : opaque_boxes)
-			append_box_ports(box, cursor, false);
+			append_box_ports(box, cursor, true);
 
 		write_be32(h_buffer, 1);
 		write_be32(h_buffer, pis.size());