mirror of https://github.com/YosysHQ/yosys.git
sim: Only check formal cells during gclk simulation updates
This is required for compatibility with non-multiclock formal semantics.
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9c6198a827
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@ -653,7 +653,7 @@ struct SimInstance
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return did_something;
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return did_something;
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}
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}
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void update_ph3()
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void update_ph3(bool check_assertions)
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{
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{
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for (auto &it : ff_database)
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for (auto &it : ff_database)
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{
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{
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@ -688,6 +688,8 @@ struct SimInstance
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}
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}
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}
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}
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if (check_assertions)
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{
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for (auto cell : formal_database)
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for (auto cell : formal_database)
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{
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{
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string label = log_id(cell);
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string label = log_id(cell);
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@ -706,9 +708,10 @@ struct SimInstance
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if (cell->type == ID($assert) && en == State::S1 && a != State::S1)
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if (cell->type == ID($assert) && en == State::S1 && a != State::S1)
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log_warning("Assert %s.%s (%s) failed.\n", hiername().c_str(), log_id(cell), label.c_str());
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log_warning("Assert %s.%s (%s) failed.\n", hiername().c_str(), log_id(cell), label.c_str());
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}
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}
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}
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for (auto it : children)
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for (auto it : children)
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it.second->update_ph3();
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it.second->update_ph3(check_assertions);
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}
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}
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void set_initstate_outputs(State state)
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void set_initstate_outputs(State state)
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@ -1116,7 +1119,7 @@ struct SimWorker : SimShared
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if (debug)
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if (debug)
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log("\n-- ph3 --\n");
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log("\n-- ph3 --\n");
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top->update_ph3();
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top->update_ph3(gclk);
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}
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}
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void initialize_stable_past()
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void initialize_stable_past()
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@ -1126,7 +1129,7 @@ struct SimWorker : SimShared
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top->update_ph1();
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top->update_ph1();
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if (debug)
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if (debug)
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log("\n-- ph3 (initialize) --\n");
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log("\n-- ph3 (initialize) --\n");
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top->update_ph3();
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top->update_ph3(false);
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}
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}
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void set_inports(pool<IdString> ports, State value)
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void set_inports(pool<IdString> ports, State value)
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