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Merge pull request #834 from YosysHQ/clifford/siminit 

Add "write_verilog -siminit"
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Clifford Wolf 2019-02-28 15:03:55 -08:00 committed by GitHub
parent e2fc18f27b 241901461a
commit f505a41b76
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GPG Key ID: 4AEE18F83AFDEB23
2 changed files with 12 additions and 3 deletions
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13
backends/verilog/verilog_backend.cc
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@ -33,7 +33,7 @@
USING_YOSYS_NAMESPACE USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN PRIVATE_NAMESPACE_BEGIN
bool verbose, norename, noattr, attr2comment, noexpr, nodec, nohex, nostr, defparam, decimal; bool verbose, norename, noattr, attr2comment, noexpr, nodec, nohex, nostr, defparam, decimal, siminit;
int auto_name_counter, auto_name_offset, auto_name_digits; int auto_name_counter, auto_name_offset, auto_name_digits;
std::map<RTLIL::IdString, int> auto_name_map; std::map<RTLIL::IdString, int> auto_name_map;
std::set<RTLIL::IdString> reg_wires, reg_ct; std::set<RTLIL::IdString> reg_wires, reg_ct;
@ -1310,7 +1310,7 @@ void dump_cell(std::ostream &f, std::string indent, RTLIL::Cell *cell)
} }
} }
if (reg_ct.count(cell->type) && cell->hasPort("\\Q")) { if (siminit && reg_ct.count(cell->type) && cell->hasPort("\\Q")) {
std::stringstream ss; std::stringstream ss;
dump_reg_init(ss, cell->getPort("\\Q")); dump_reg_init(ss, cell->getPort("\\Q"));
if (!ss.str().empty()) { if (!ss.str().empty()) {
@ -1607,6 +1607,10 @@ struct VerilogBackend : public Backend {
log(" without this option all internal cells are converted to Verilog\n"); log(" without this option all internal cells are converted to Verilog\n");
log(" expressions.\n"); log(" expressions.\n");
log("\n"); log("\n");
log(" -siminit\n");
log(" add initial statements with hierarchical refs to initialize FFs when\n");
log(" in -noexpr mode.\n");
log("\n");
log(" -nodec\n"); log(" -nodec\n");
log(" 32-bit constant values are by default dumped as decimal numbers,\n"); log(" 32-bit constant values are by default dumped as decimal numbers,\n");
log(" not bit pattern. This option deactivates this feature and instead\n"); log(" not bit pattern. This option deactivates this feature and instead\n");
@ -1663,6 +1667,7 @@ struct VerilogBackend : public Backend {
nostr = false; nostr = false;
defparam = false; defparam = false;
decimal = false; decimal = false;
siminit = false;
auto_prefix = ""; auto_prefix = "";
bool blackboxes = false; bool blackboxes = false;
@ -1739,6 +1744,10 @@ struct VerilogBackend : public Backend {
decimal = true; decimal = true;
continue; continue;
} }
if (arg == "-siminit") {
siminit = true;
continue;
}
if (arg == "-blackboxes") { if (arg == "-blackboxes") {
blackboxes = true; blackboxes = true;
continue; continue;

2
tests/tools/autotest.sh
View File

@ -8,7 +8,7 @@ verbose=false
keeprunning=false keeprunning=false
makejmode=false makejmode=false
frontend="verilog" frontend="verilog"
backend_opts="-noattr -noexpr" backend_opts="-noattr -noexpr -siminit"
autotb_opts="" autotb_opts=""
include_opts="" include_opts=""
xinclude_opts="" xinclude_opts=""