mirror of https://github.com/YosysHQ/yosys.git
Merge pull request #4815 from YosysHQ/verific_bounds_fix
Verific frontend: fix `top_bound`/`bottom_bound` attributes
This commit is contained in:
N. Engelhardt
GitHub
commit
f384eac28b
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@ -407,7 +407,7 @@ static const std::string verific_unescape(const char *value)
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}
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#endif
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void VerificImporter::import_attributes(dict<RTLIL::IdString, RTLIL::Const> &attributes, DesignObj *obj, Netlist *nl)
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void VerificImporter::import_attributes(dict<RTLIL::IdString, RTLIL::Const> &attributes, DesignObj *obj, Netlist *nl, int wire_width_hint)
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{
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if (!obj)
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return;
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@ -433,10 +433,18 @@ void VerificImporter::import_attributes(dict<RTLIL::IdString, RTLIL::Const> &att
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auto type_range = nl->GetTypeRange(obj->Name());
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if (!type_range)
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return;
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if (type_range->IsTypeScalar()) {
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if (nl->IsFromVhdl() && type_range->IsTypeScalar()) {
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const long long bottom_bound = type_range->GetScalarRangeLeftBound();
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const long long top_bound = type_range->GetScalarRangeRightBound();
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const unsigned bit_width = type_range->NumElements();
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int bit_width = type_range->LeftRangeBound()+1;
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if (bit_width <= 0) { // VHDL null range
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if (wire_width_hint >= 0)
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bit_width = wire_width_hint;
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else
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bit_width = 64; //fallback, currently largest integer width that verific will allow (in vhdl2019 mode)
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} else {
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if (wire_width_hint >= 0) log_assert(bit_width == wire_width_hint);
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}
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RTLIL::Const bottom_const(bottom_bound, bit_width);
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RTLIL::Const top_const(top_bound, bit_width);
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if (bottom_bound < 0 || top_bound < 0) {
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@ -1499,7 +1507,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
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log(" importing port %s.\n", port->Name());
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RTLIL::Wire *wire = module->addWire(RTLIL::escape_id(port->Name()));
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import_attributes(wire->attributes, port, nl);
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import_attributes(wire->attributes, port, nl, 1);
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wire->port_id = nl->IndexOf(port) + 1;
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@ -1527,11 +1535,11 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
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RTLIL::Wire *wire = module->addWire(RTLIL::escape_id(portbus->Name()), portbus->Size());
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wire->start_offset = min(portbus->LeftIndex(), portbus->RightIndex());
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wire->upto = portbus->IsUp();
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import_attributes(wire->attributes, portbus, nl);
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import_attributes(wire->attributes, portbus, nl, portbus->Size());
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SetIter si ;
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Port *port ;
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FOREACH_PORT_OF_PORTBUS(portbus, si, port) {
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import_attributes(wire->attributes, port->GetNet(), nl);
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import_attributes(wire->attributes, port->GetNet(), nl, portbus->Size());
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break;
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}
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bool portbus_input = portbus->GetDir() == DIR_INOUT || portbus->GetDir() == DIR_IN;
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@ -1693,7 +1701,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
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log(" importing net %s as %s.\n", net->Name(), log_id(wire_name));
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RTLIL::Wire *wire = module->addWire(wire_name);
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import_attributes(wire->attributes, net, nl);
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import_attributes(wire->attributes, net, nl, 1);
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net_map[net] = wire;
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}
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@ -1722,10 +1730,10 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
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MapIter mibus;
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FOREACH_NET_OF_NETBUS(netbus, mibus, net) {
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if (net)
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import_attributes(wire->attributes, net, nl);
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import_attributes(wire->attributes, net, nl, netbus->Size());
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break;
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}
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import_attributes(wire->attributes, netbus, nl);
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import_attributes(wire->attributes, netbus, nl, netbus->Size());
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RTLIL::Const initval = Const(State::Sx, GetSize(wire));
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bool initval_valid = false;
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@ -81,7 +81,7 @@ struct VerificImporter
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RTLIL::SigBit net_map_at(Verific::Net *net);
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RTLIL::IdString new_verific_id(Verific::DesignObj *obj);
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void import_attributes(dict<RTLIL::IdString, RTLIL::Const> &attributes, Verific::DesignObj *obj, Verific::Netlist *nl = nullptr);
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void import_attributes(dict<RTLIL::IdString, RTLIL::Const> &attributes, Verific::DesignObj *obj, Verific::Netlist *nl = nullptr, int wire_width_hint = -1);
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RTLIL::SigBit netToSigBit(Verific::Net *net);
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RTLIL::SigSpec operatorInput(Verific::Instance *inst);
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@ -0,0 +1,45 @@
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typedef enum {IDLE, RUN, STOP} state_t;
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typedef struct {
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logic [7:0] field1;
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int field2;
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} my_struct_t;
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// Submodule to handle the interface ports
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module submodule (
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my_ifc i_ifc,
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my_ifc o_ifc
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);
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// Connect the interface signals
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assign o_ifc.data = i_ifc.data;
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endmodule
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module test (
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input i_a,
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output o_a,
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input [0:0] i_b,
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output [0:0] o_b,
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input [3:0] i_c,
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output [3:0] o_c,
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input logic i_d,
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output logic o_d,
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input bit [7:0] i_e,
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output bit [7:0] o_e,
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input int i_f,
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output int o_f,
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input state_t i_h,
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output state_t o_h,
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input my_struct_t i_i,
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output my_struct_t o_i
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);
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assign o_a = i_a;
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assign o_b = i_b;
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assign o_c = i_c;
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assign o_d = i_d;
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assign o_e = i_e;
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assign o_f = i_f;
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assign o_h = i_h;
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assign o_i = i_i;
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endmodule
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@ -2,17 +2,108 @@ library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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entity work is
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entity test is
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Port (
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a : in INTEGER range -5 to 10;
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b : out INTEGER range -6 to 11
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);
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end entity work;
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-- BIT type
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bit_in : in BIT;
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bit_out : out BIT;
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architecture Behavioral of work is
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-- BIT_VECTOR type
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bit_vector_in : in BIT_VECTOR(3 downto 0);
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bit_vector_out : out BIT_VECTOR(3 downto 0);
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-- BIT_VECTOR type with to index
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bit_vector_in_to : in BIT_VECTOR(0 to 3);
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bit_vector_out_to : out BIT_VECTOR(0 to 3);
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-- STD_ULOGIC type
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std_ulogic_in : in STD_ULOGIC;
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std_ulogic_out : out STD_ULOGIC;
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-- STD_ULOGIC_VECTOR type
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std_ulogic_vector_in : in STD_ULOGIC_VECTOR(3 downto 0);
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std_ulogic_vector_out : out STD_ULOGIC_VECTOR(3 downto 0);
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-- STD_ULOGIC_VECTOR type with to index
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std_ulogic_vector_in_to : in STD_ULOGIC_VECTOR(0 to 3);
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std_ulogic_vector_out_to : out STD_ULOGIC_VECTOR(0 to 3);
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-- STD_LOGIC type
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std_logic_in : in STD_LOGIC;
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std_logic_out : out STD_LOGIC;
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-- STD_LOGIC_VECTOR type
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std_logic_vector_in : in STD_LOGIC_VECTOR(3 downto 0);
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std_logic_vector_out : out STD_LOGIC_VECTOR(3 downto 0);
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-- STD_LOGIC_VECTOR type with to index
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std_logic_vector_in_to : in STD_LOGIC_VECTOR(0 to 3);
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std_logic_vector_out_to : out STD_LOGIC_VECTOR(0 to 3);
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-- SIGNED type
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signed_in : in SIGNED(3 downto 0);
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signed_out : out SIGNED(3 downto 0);
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-- SIGNED type with to index
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signed_in_to : in SIGNED(0 to 3);
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signed_out_to : out SIGNED(0 to 3);
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-- UNSIGNED type
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unsigned_in : in UNSIGNED(3 downto 0);
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unsigned_out : out UNSIGNED(3 downto 0);
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-- UNSIGNED type with to index
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unsigned_in_to : in UNSIGNED(0 to 3);
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unsigned_out_to : out UNSIGNED(0 to 3);
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-- INTEGER type without range
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integer_in : in INTEGER;
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integer_out : out INTEGER;
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-- INTEGER type with range
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integer_with_range_in : in INTEGER range -5 to 10;
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integer_with_range_out : out INTEGER range -6 to 10;
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-- INTEGER type with single value range
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integer_single_value_in : in INTEGER range 5 to 5;
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integer_single_value_out : out INTEGER range 5 to 5;
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-- INTEGER type with null range
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integer_null_range_in : in INTEGER range 7 to -1;
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integer_null_range_out : out INTEGER range 0 to -1;
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-- NATURAL type
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natural_in : in NATURAL;
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natural_out : out NATURAL;
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-- POSITIVE type
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positive_in : in POSITIVE;
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positive_out : out POSITIVE
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);
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end entity test;
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architecture Behavioral of test is
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signal integer_with_range : INTEGER range -1 to 100;
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begin
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process(a)
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begin
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b <= a;
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end process;
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bit_out <= bit_in;
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bit_vector_out <= bit_vector_in;
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bit_vector_out_to <= bit_vector_in_to;
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std_ulogic_out <= std_ulogic_in;
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std_ulogic_vector_out <= std_ulogic_vector_in;
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std_ulogic_vector_out_to <= std_ulogic_vector_in_to;
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std_logic_out <= std_logic_in;
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std_logic_vector_out <= std_logic_vector_in;
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std_logic_vector_out_to <= std_logic_vector_in_to;
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signed_out <= signed_in;
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signed_out_to <= signed_in_to;
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unsigned_out <= unsigned_in;
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unsigned_out_to <= unsigned_in_to;
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integer_with_range_out <= integer_with_range_in;
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integer_out <= integer_in;
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integer_single_value_out <= integer_single_value_in;
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integer_null_range_out <= integer_null_range_in;
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natural_out <= natural_in;
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positive_out <= positive_in;
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integer_with_range <= 42;
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end architecture Behavioral;
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@ -1,6 +1,168 @@
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read -vhdl bounds.vhd
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verific -import work
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select -assert-count 1 a:bottom_bound=5'bs11011
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select -assert-count 1 a:top_bound=5'bs01010
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select -assert-count 1 a:bottom_bound=5'bs11010
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select -assert-count 1 a:top_bound=5'bs01011
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hierarchy -top test
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# bit: not a scalar type
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select -assert-count 0 w:bit_in a:bottom_bound %i
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select -assert-count 0 w:bit_in a:top_bound %i
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select -assert-count 0 w:bit_out a:bottom_bound %i
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select -assert-count 0 w:bit_out a:top_bound %i
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# bit_vector: not a scalar type
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select -assert-count 0 w:bit_vector_in a:bottom_bound %i
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select -assert-count 0 w:bit_vector_in a:top_bound %i
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select -assert-count 0 w:bit_vector_out a:bottom_bound %i
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select -assert-count 0 w:bit_vector_out a:top_bound %i
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# bit_vector with to index: not a scalar type
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select -assert-count 0 w:bit_vector_in_to a:bottom_bound %i
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select -assert-count 0 w:bit_vector_in_to a:top_bound %i
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select -assert-count 0 w:bit_vector_out_to a:bottom_bound %i
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select -assert-count 0 w:bit_vector_out_to a:top_bound %i
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# std_ulogic: not a scalar type
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select -assert-count 0 w:std_ulogic_in a:bottom_bound %i
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select -assert-count 0 w:std_ulogic_in a:top_bound %i
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select -assert-count 0 w:std_ulogic_out a:bottom_bound %i
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select -assert-count 0 w:std_ulogic_out a:top_bound %i
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# std_ulogic_vector: not a scalar type
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select -assert-count 0 w:std_ulogic_vector_in a:bottom_bound %i
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select -assert-count 0 w:std_ulogic_vector_in a:top_bound %i
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select -assert-count 0 w:std_ulogic_vector_out a:bottom_bound %i
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select -assert-count 0 w:std_ulogic_vector_out a:top_bound %i
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# std_ulogic_vector with to index: not a scalar type
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select -assert-count 0 w:std_ulogic_vector_in_to a:bottom_bound %i
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select -assert-count 0 w:std_ulogic_vector_in_to a:top_bound %i
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select -assert-count 0 w:std_ulogic_vector_out_to a:bottom_bound %i
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select -assert-count 0 w:std_ulogic_vector_out_to a:top_bound %i
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# std_logic: not a scalar type
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select -assert-count 0 w:std_logic_in a:bottom_bound %i
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select -assert-count 0 w:std_logic_in a:top_bound %i
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select -assert-count 0 w:std_logic_out a:bottom_bound %i
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select -assert-count 0 w:std_logic_out a:top_bound %i
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# std_logic_vector: not a scalar type
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select -assert-count 0 w:std_logic_vector_in a:bottom_bound %i
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select -assert-count 0 w:std_logic_vector_in a:top_bound %i
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select -assert-count 0 w:std_logic_vector_out a:bottom_bound %i
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select -assert-count 0 w:std_logic_vector_out a:top_bound %i
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# std_logic_vector with to index: not a scalar type
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select -assert-count 0 w:std_logic_vector_in_to a:bottom_bound %i
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select -assert-count 0 w:std_logic_vector_in_to a:top_bound %i
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select -assert-count 0 w:std_logic_vector_out_to a:bottom_bound %i
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select -assert-count 0 w:std_logic_vector_out_to a:top_bound %i
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# signed: not a scalar type
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select -assert-count 0 w:signed_in a:bottom_bound %i
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select -assert-count 0 w:signed_in a:top_bound %i
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select -assert-count 0 w:signed_out a:bottom_bound %i
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select -assert-count 0 w:signed_out a:top_bound %i
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# signed with to index: not a scalar type
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select -assert-count 0 w:signed_in_to a:bottom_bound %i
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select -assert-count 0 w:signed_in_to a:top_bound %i
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select -assert-count 0 w:signed_out_to a:bottom_bound %i
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select -assert-count 0 w:signed_out_to a:top_bound %i
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# unsigned: not a scalar type
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select -assert-count 0 w:unsigned_in a:bottom_bound %i
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select -assert-count 0 w:unsigned_in a:top_bound %i
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select -assert-count 0 w:unsigned_out a:bottom_bound %i
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select -assert-count 0 w:unsigned_out a:top_bound %i
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# unsigned with to index: not a scalar type
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select -assert-count 0 w:unsigned_in_to a:bottom_bound %i
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select -assert-count 0 w:unsigned_in_to a:top_bound %i
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select -assert-count 0 w:unsigned_out_to a:bottom_bound %i
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select -assert-count 0 w:unsigned_out_to a:top_bound %i
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# integer: scalar type
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select -assert-count 1 w:integer_in a:bottom_bound=32'b10000000000000000000000000000000 %i
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select -assert-count 1 w:integer_in a:top_bound=32'b01111111111111111111111111111111 %i
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select -assert-count 1 w:integer_out a:bottom_bound=32'b10000000000000000000000000000000 %i
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select -assert-count 1 w:integer_out a:top_bound=32'b01111111111111111111111111111111 %i
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# integer with range: scalar type
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select -assert-count 1 w:integer_with_range_in a:bottom_bound=5'bs11011 %i
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select -assert-count 1 w:integer_with_range_in a:top_bound=5'bs01010 %i
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select -assert-count 1 w:integer_with_range_out a:bottom_bound=5'bs11010 %i
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select -assert-count 1 w:integer_with_range_out a:top_bound=5'bs01010 %i
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# integer with single value range: scalar type
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select -assert-count 1 w:integer_single_value_in a:bottom_bound=3'bs101 %i
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select -assert-count 1 w:integer_single_value_in a:top_bound=3'bs101 %i
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select -assert-count 1 w:integer_single_value_out a:bottom_bound=3'bs101 %i
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select -assert-count 1 w:integer_single_value_out a:top_bound=3'bs101 %i
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# integer with null range: scalar type
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select -assert-count 1 w:integer_null_range_in a:bottom_bound=4'bs0111 %i
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select -assert-count 1 w:integer_null_range_in a:top_bound=4'bs1111 %i
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select -assert-count 1 w:integer_null_range_out a:bottom_bound=1'bs0 %i
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select -assert-count 1 w:integer_null_range_out a:top_bound=1'bs1 %i
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# natural: scalar type
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select -assert-count 1 w:natural_in a:bottom_bound=31'b0000000000000000000000000000000 %i
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select -assert-count 1 w:natural_in a:top_bound=31'b1111111111111111111111111111111 %i
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select -assert-count 1 w:natural_out a:bottom_bound=31'b0000000000000000000000000000000 %i
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select -assert-count 1 w:natural_out a:top_bound=31'b1111111111111111111111111111111 %i
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# positive: scalar type
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select -assert-count 1 w:positive_in a:bottom_bound=31'b0000000000000000000000000000001 %i
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select -assert-count 1 w:positive_in a:top_bound=31'b1111111111111111111111111111111 %i
|
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select -assert-count 1 w:positive_out a:bottom_bound=31'b0000000000000000000000000000001 %i
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select -assert-count 1 w:positive_out a:top_bound=31'b1111111111111111111111111111111 %i
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design -reset
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read -vhdl2019 bounds.vhd
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hierarchy -top test
|
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## integer size changed in VHDL 2019
|
||||
# integer: scalar type
|
||||
select -assert-count 1 w:integer_in a:bottom_bound=64'b1000000000000000000000000000000000000000000000000000000000000000 %i
|
||||
select -assert-count 1 w:integer_in a:top_bound=64'b0111111111111111111111111111111111111111111111111111111111111111 %i
|
||||
select -assert-count 1 w:integer_out a:bottom_bound=64'b1000000000000000000000000000000000000000000000000000000000000000 %i
|
||||
select -assert-count 1 w:integer_out a:top_bound=64'b0111111111111111111111111111111111111111111111111111111111111111 %i
|
||||
|
||||
# natural: scalar type
|
||||
select -assert-count 1 w:natural_in a:bottom_bound=63'b000000000000000000000000000000000000000000000000000000000000000 %i
|
||||
select -assert-count 1 w:natural_in a:top_bound=63'b111111111111111111111111111111111111111111111111111111111111111 %i
|
||||
select -assert-count 1 w:natural_out a:bottom_bound=63'b000000000000000000000000000000000000000000000000000000000000000 %i
|
||||
select -assert-count 1 w:natural_out a:top_bound=63'b111111111111111111111111111111111111111111111111111111111111111 %i
|
||||
|
||||
# positive: scalar type
|
||||
select -assert-count 1 w:positive_in a:bottom_bound=63'b000000000000000000000000000000000000000000000000000000000000001 %i
|
||||
select -assert-count 1 w:positive_in a:top_bound=63'b111111111111111111111111111111111111111111111111111111111111111 %i
|
||||
select -assert-count 1 w:positive_out a:bottom_bound=63'b000000000000000000000000000000000000000000000000000000000000001 %i
|
||||
select -assert-count 1 w:positive_out a:top_bound=63'b111111111111111111111111111111111111111111111111111111111111111 %i
|
||||
|
||||
## ranged integer sizes should be unaffected
|
||||
# integer with range: scalar type
|
||||
select -assert-count 1 w:integer_with_range_in a:bottom_bound=5'bs11011 %i
|
||||
select -assert-count 1 w:integer_with_range_in a:top_bound=5'bs01010 %i
|
||||
select -assert-count 1 w:integer_with_range_out a:bottom_bound=5'bs11010 %i
|
||||
select -assert-count 1 w:integer_with_range_out a:top_bound=5'bs01010 %i
|
||||
|
||||
# integer with single value range: scalar type
|
||||
select -assert-count 1 w:integer_single_value_in a:bottom_bound=3'bs101 %i
|
||||
select -assert-count 1 w:integer_single_value_in a:top_bound=3'bs101 %i
|
||||
select -assert-count 1 w:integer_single_value_out a:bottom_bound=3'bs101 %i
|
||||
select -assert-count 1 w:integer_single_value_out a:top_bound=3'bs101 %i
|
||||
|
||||
# integer with null range: scalar type
|
||||
select -assert-count 1 w:integer_null_range_in a:bottom_bound=4'bs0111 %i
|
||||
select -assert-count 1 w:integer_null_range_in a:top_bound=4'bs1111 %i
|
||||
select -assert-count 1 w:integer_null_range_out a:bottom_bound=1'bs0 %i
|
||||
select -assert-count 1 w:integer_null_range_out a:top_bound=1'bs1 %i
|
||||
|
||||
|
||||
design -reset
|
||||
read -sv bounds.sv
|
||||
hierarchy -top test
|
||||
|
||||
## bounds should not be generated for SV
|
||||
select -assert-count none a:bottom_bound
|
||||
select -assert-count none a:top_bound
|
||||
|
|
|
|||
Loading…
Reference in New Issue