mirror of https://github.com/YosysHQ/yosys.git
bound attributes: handle vhdl null ranges
This commit is contained in:
N. Engelhardt
parent
03033ab6d4
commit
378864d33b
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@ -407,7 +407,7 @@ static const std::string verific_unescape(const char *value)
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}
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#endif
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void VerificImporter::import_attributes(dict<RTLIL::IdString, RTLIL::Const> &attributes, DesignObj *obj, Netlist *nl)
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void VerificImporter::import_attributes(dict<RTLIL::IdString, RTLIL::Const> &attributes, DesignObj *obj, Netlist *nl, int wire_width_hint)
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{
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if (!obj)
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return;
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@ -436,7 +436,15 @@ void VerificImporter::import_attributes(dict<RTLIL::IdString, RTLIL::Const> &att
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if (nl->IsFromVhdl() && type_range->IsTypeScalar()) {
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const long long bottom_bound = type_range->GetScalarRangeLeftBound();
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const long long top_bound = type_range->GetScalarRangeRightBound();
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const unsigned bit_width = type_range->NumElements();
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int bit_width = type_range->LeftRangeBound()+1;
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if (bit_width <= 0) { // VHDL null range
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if (wire_width_hint >= 0)
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bit_width = wire_width_hint;
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else
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bit_width = 64; //fallback, currently largest integer width that verific will allow (in vhdl2019 mode)
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} else {
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if (wire_width_hint >= 0) log_assert(bit_width == wire_width_hint);
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}
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RTLIL::Const bottom_const(bottom_bound, bit_width);
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RTLIL::Const top_const(top_bound, bit_width);
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if (bottom_bound < 0 || top_bound < 0) {
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@ -1499,7 +1507,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
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log(" importing port %s.\n", port->Name());
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RTLIL::Wire *wire = module->addWire(RTLIL::escape_id(port->Name()));
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import_attributes(wire->attributes, port, nl);
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import_attributes(wire->attributes, port, nl, 1);
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wire->port_id = nl->IndexOf(port) + 1;
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@ -1527,11 +1535,11 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
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RTLIL::Wire *wire = module->addWire(RTLIL::escape_id(portbus->Name()), portbus->Size());
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wire->start_offset = min(portbus->LeftIndex(), portbus->RightIndex());
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wire->upto = portbus->IsUp();
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import_attributes(wire->attributes, portbus, nl);
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import_attributes(wire->attributes, portbus, nl, portbus->Size());
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SetIter si ;
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Port *port ;
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FOREACH_PORT_OF_PORTBUS(portbus, si, port) {
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import_attributes(wire->attributes, port->GetNet(), nl);
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import_attributes(wire->attributes, port->GetNet(), nl, portbus->Size());
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break;
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}
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bool portbus_input = portbus->GetDir() == DIR_INOUT || portbus->GetDir() == DIR_IN;
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@ -1693,7 +1701,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
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log(" importing net %s as %s.\n", net->Name(), log_id(wire_name));
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RTLIL::Wire *wire = module->addWire(wire_name);
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import_attributes(wire->attributes, net, nl);
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import_attributes(wire->attributes, net, nl, 1);
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net_map[net] = wire;
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}
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@ -1722,10 +1730,10 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
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MapIter mibus;
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FOREACH_NET_OF_NETBUS(netbus, mibus, net) {
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if (net)
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import_attributes(wire->attributes, net, nl);
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import_attributes(wire->attributes, net, nl, netbus->Size());
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break;
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}
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import_attributes(wire->attributes, netbus, nl);
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import_attributes(wire->attributes, netbus, nl, netbus->Size());
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RTLIL::Const initval = Const(State::Sx, GetSize(wire));
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bool initval_valid = false;
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@ -81,7 +81,7 @@ struct VerificImporter
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RTLIL::SigBit net_map_at(Verific::Net *net);
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RTLIL::IdString new_verific_id(Verific::DesignObj *obj);
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void import_attributes(dict<RTLIL::IdString, RTLIL::Const> &attributes, Verific::DesignObj *obj, Verific::Netlist *nl = nullptr);
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void import_attributes(dict<RTLIL::IdString, RTLIL::Const> &attributes, Verific::DesignObj *obj, Verific::Netlist *nl = nullptr, int wire_width_hint = -1);
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RTLIL::SigBit netToSigBit(Verific::Net *net);
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RTLIL::SigSpec operatorInput(Verific::Instance *inst);
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@ -1,14 +1,45 @@
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module test (
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input ia,
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output oa,
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input [0:0] ib,
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output [0:0] ob,
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input [3:0] ic,
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output [3:0] oc
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);
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typedef enum {IDLE, RUN, STOP} state_t;
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assign oa = ia;
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assign ob = ib;
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assign oc = ic;
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typedef struct {
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logic [7:0] field1;
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int field2;
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} my_struct_t;
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// Submodule to handle the interface ports
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module submodule (
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my_ifc i_ifc,
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my_ifc o_ifc
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);
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// Connect the interface signals
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assign o_ifc.data = i_ifc.data;
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endmodule
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module test (
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input i_a,
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output o_a,
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input [0:0] i_b,
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output [0:0] o_b,
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input [3:0] i_c,
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output [3:0] o_c,
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input logic i_d,
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output logic o_d,
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input bit [7:0] i_e,
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output bit [7:0] o_e,
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input int i_f,
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output int o_f,
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input state_t i_h,
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output state_t o_h,
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input my_struct_t i_i,
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output my_struct_t o_i
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);
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assign o_a = i_a;
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assign o_b = i_b;
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assign o_c = i_c;
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assign o_d = i_d;
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assign o_e = i_e;
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assign o_f = i_f;
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assign o_h = i_h;
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assign o_i = i_i;
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endmodule
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@ -83,6 +83,7 @@ entity test is
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end entity test;
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architecture Behavioral of test is
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signal integer_with_range : INTEGER range -1 to 100;
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begin
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bit_out <= bit_in;
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bit_vector_out <= bit_vector_in;
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@ -103,4 +104,6 @@ begin
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integer_null_range_out <= integer_null_range_in;
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natural_out <= natural_in;
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positive_out <= positive_in;
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integer_with_range <= 42;
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end architecture Behavioral;
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@ -98,10 +98,10 @@ select -assert-count 1 w:integer_single_value_out a:bottom_bound=3'bs101 %i
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select -assert-count 1 w:integer_single_value_out a:top_bound=3'bs101 %i
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# integer with null range: scalar type
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# select -assert-count 1 w:integer_null_range_in a:bottom_bound=4'bs0111 %i
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# select -assert-count 1 w:integer_null_range_in a:top_bound=4'bs1111 %i
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select -assert-count 1 w:integer_null_range_out a:bottom_bound=2'bs00 %i
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select -assert-count 1 w:integer_null_range_out a:top_bound=2'bs11 %i
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select -assert-count 1 w:integer_null_range_in a:bottom_bound=4'bs0111 %i
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select -assert-count 1 w:integer_null_range_in a:top_bound=4'bs1111 %i
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select -assert-count 1 w:integer_null_range_out a:bottom_bound=1'bs0 %i
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select -assert-count 1 w:integer_null_range_out a:top_bound=1'bs1 %i
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# natural: scalar type
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select -assert-count 1 w:natural_in a:bottom_bound=31'b0000000000000000000000000000000 %i
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@ -116,11 +116,11 @@ select -assert-count 1 w:positive_out a:bottom_bound=31'b00000000000000000000000
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select -assert-count 1 w:positive_out a:top_bound=31'b1111111111111111111111111111111 %i
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# integer size changed in VHDL 2019
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design -reset
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read -vhdl2019 bounds.vhd
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hierarchy -top test
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## integer size changed in VHDL 2019
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# integer: scalar type
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select -assert-count 1 w:integer_in a:bottom_bound=64'b1000000000000000000000000000000000000000000000000000000000000000 %i
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select -assert-count 1 w:integer_in a:top_bound=64'b0111111111111111111111111111111111111111111111111111111111111111 %i
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@ -139,9 +139,30 @@ select -assert-count 1 w:positive_in a:top_bound=63'b111111111111111111111111111
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select -assert-count 1 w:positive_out a:bottom_bound=63'b000000000000000000000000000000000000000000000000000000000000001 %i
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select -assert-count 1 w:positive_out a:top_bound=63'b111111111111111111111111111111111111111111111111111111111111111 %i
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## ranged integer sizes should be unaffected
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# integer with range: scalar type
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select -assert-count 1 w:integer_with_range_in a:bottom_bound=5'bs11011 %i
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select -assert-count 1 w:integer_with_range_in a:top_bound=5'bs01010 %i
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select -assert-count 1 w:integer_with_range_out a:bottom_bound=5'bs11010 %i
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select -assert-count 1 w:integer_with_range_out a:top_bound=5'bs01010 %i
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# integer with single value range: scalar type
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select -assert-count 1 w:integer_single_value_in a:bottom_bound=3'bs101 %i
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select -assert-count 1 w:integer_single_value_in a:top_bound=3'bs101 %i
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select -assert-count 1 w:integer_single_value_out a:bottom_bound=3'bs101 %i
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select -assert-count 1 w:integer_single_value_out a:top_bound=3'bs101 %i
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# integer with null range: scalar type
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select -assert-count 1 w:integer_null_range_in a:bottom_bound=4'bs0111 %i
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select -assert-count 1 w:integer_null_range_in a:top_bound=4'bs1111 %i
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select -assert-count 1 w:integer_null_range_out a:bottom_bound=1'bs0 %i
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select -assert-count 1 w:integer_null_range_out a:top_bound=1'bs1 %i
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design -reset
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read -sv bounds.sv
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hierarchy -top test
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## bounds should not be generated for SV
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select -assert-count none a:bottom_bound
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select -assert-count none a:top_bound
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