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Added CellEdgesDatabase API

This commit is contained in:
Clifford Wolf 2016-07-24 13:59:57 +02:00
parent 54966679df
commit f162b858f2
4 changed files with 250 additions and 1 deletions
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4
Makefile
View File

@ -279,7 +279,9 @@ $(eval $(call add_include_file,passes/fsm/fsmdata.h))
$(eval $(call add_include_file,frontends/ast/ast.h))
$(eval $(call add_include_file,backends/ilang/ilang_backend.h))
OBJS += kernel/driver.o kernel/register.o kernel/rtlil.o kernel/log.o kernel/calc.o kernel/yosys.o kernel/cellaigs.o
OBJS += kernel/driver.o kernel/register.o kernel/rtlil.o kernel/log.o kernel/calc.o kernel/yosys.o
OBJS += kernel/cellaigs.o kernel/celledges.o
kernel/log.o: CXXFLAGS += -DYOSYS_SRC='"$(YOSYS_SRC)"'
kernel/yosys.o: CXXFLAGS += -DYOSYS_DATDIR='"$(DATDIR)"'

88
kernel/celledges.cc Normal file
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@ -0,0 +1,88 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
#include "kernel/celledges.h"
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
void add_bitwise_unary_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
{
IdString A = "\\A", Y = "\\Y";
bool is_signed = cell->getParam("\\A_SIGNED").as_bool();
int a_width = GetSize(cell->getPort(A));
int y_width = GetSize(cell->getPort(Y));
for (int i = 0; i < y_width; i++)
{
if (i < a_width)
db->add_edge(cell, A, i, Y, i);
else if (is_signed && a_width > 0)
db->add_edge(cell, A, a_width-1, Y, i);
}
}
void add_bitwise_binary_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
{
IdString A = "\\A", B = "\\B", Y = "\\Y";
bool is_signed = cell->getParam("\\A_SIGNED").as_bool();
int a_width = GetSize(cell->getPort(A));
int b_width = GetSize(cell->getPort(B));
int y_width = GetSize(cell->getPort(Y));
if (cell->type == "$and" && !is_signed) {
if (a_width > b_width)
a_width = b_width;
else
b_width = a_width;
}
for (int i = 0; i < y_width; i++)
{
if (i < a_width)
db->add_edge(cell, A, i, Y, i);
else if (is_signed && a_width > 0)
db->add_edge(cell, A, a_width-1, Y, i);
if (i < b_width)
db->add_edge(cell, B, i, Y, i);
else if (is_signed && b_width > 0)
db->add_edge(cell, B, b_width-1, Y, i);
}
}
PRIVATE_NAMESPACE_END
bool YOSYS_NAMESPACE_PREFIX AbstractCellEdgesDatabase::add_cell(RTLIL::Cell *cell)
{
if (cell->type.in("$not", "$pos")) {
add_bitwise_unary_op(this, cell);
return true;
}
if (cell->type.in("$and", "$or", "$xor", "$xnor")) {
add_bitwise_binary_op(this, cell);
return true;
}
return false;
}

63
kernel/celledges.h Normal file
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@ -0,0 +1,63 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
#ifndef CELLEDGES_H
#define CELLEDGES_H
#include "kernel/yosys.h"
#include "kernel/sigtools.h"
YOSYS_NAMESPACE_BEGIN
struct AbstractCellEdgesDatabase
{
virtual ~AbstractCellEdgesDatabase() { }
virtual void add_edge(RTLIL::Cell *cell, RTLIL::IdString from_port, int from_bit, RTLIL::IdString to_port, int to_bit) = 0;
bool add_cell(RTLIL::Cell *cell);
};
struct FwdCellEdgesDatabase : AbstractCellEdgesDatabase
{
SigMap &sigmap;
dict<SigBit, pool<SigBit>> db;
FwdCellEdgesDatabase(SigMap &sigmap) : sigmap(sigmap) { }
virtual void add_edge(RTLIL::Cell *cell, RTLIL::IdString from_port, int from_bit, RTLIL::IdString to_port, int to_bit) override {
SigBit from_sigbit = sigmap(cell->getPort(from_port)[from_bit]);
SigBit to_sigbit = sigmap(cell->getPort(to_port)[to_bit]);
db[from_sigbit].insert(to_sigbit);
}
};
struct RevCellEdgesDatabase : AbstractCellEdgesDatabase
{
SigMap &sigmap;
dict<SigBit, pool<SigBit>> db;
RevCellEdgesDatabase(SigMap &sigmap) : sigmap(sigmap) { }
virtual void add_edge(RTLIL::Cell *cell, RTLIL::IdString from_port, int from_bit, RTLIL::IdString to_port, int to_bit) override {
SigBit from_sigbit = sigmap(cell->getPort(from_port)[from_bit]);
SigBit to_sigbit = sigmap(cell->getPort(to_port)[to_bit]);
db[to_sigbit].insert(from_sigbit);
}
};
YOSYS_NAMESPACE_END
#endif

96
passes/tests/test_cell.cc
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@ -21,6 +21,7 @@
#include "kernel/yosys.h"
#include "kernel/satgen.h"
#include "kernel/consteval.h"
#include "kernel/celledges.h"
#include "kernel/macc.h"
#include <algorithm>
@ -305,6 +306,90 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type,
cell->check();
}
static void run_edges_test(RTLIL::Design *design, bool verbose)
{
Module *module = *design->modules().begin();
Cell *cell = *module->cells().begin();
ezSatPtr ezptr;
ezSAT &ez = *ezptr.get();
SigMap sigmap(module);
SatGen satgen(&ez, &sigmap);
FwdCellEdgesDatabase edges_db(sigmap);
edges_db.add_cell(cell);
dict<SigBit, pool<SigBit>> satgen_db;
satgen.setContext(&sigmap, "X:");
satgen.importCell(cell);
satgen.setContext(&sigmap, "Y:");
satgen.importCell(cell);
vector<tuple<SigBit, int, int>> input_db, output_db;
for (auto &conn : cell->connections())
{
SigSpec bits = sigmap(conn.second);
satgen.setContext(&sigmap, "X:");
std::vector<int> xbits = satgen.importSigSpec(bits);
satgen.setContext(&sigmap, "Y:");
std::vector<int> ybits = satgen.importSigSpec(bits);
for (int i = 0; i < GetSize(bits); i++)
if (cell->input(conn.first))
input_db.emplace_back(bits[i], xbits[i], ybits[i]);
else
output_db.emplace_back(bits[i], xbits[i], ybits[i]);
}
if (verbose)
log("\nSAT solving for all edges:\n");
for (int i = 0; i < GetSize(input_db); i++)
{
SigBit inbit = std::get<0>(input_db[i]);
if (verbose)
log(" Testing input signal %s:\n", log_signal(inbit));
vector<int> xinbits, yinbits;
for (int k = 0; k < GetSize(input_db); k++)
if (k != i) {
xinbits.push_back(std::get<1>(input_db[k]));
yinbits.push_back(std::get<2>(input_db[k]));
}
int xyinbit_ok = ez.vec_eq(xinbits, yinbits);
for (int k = 0; k < GetSize(output_db); k++)
{
SigBit outbit = std::get<0>(output_db[k]);
int xoutbit = std::get<1>(output_db[k]);
int youtbit = std::get<2>(output_db[k]);
bool is_edge = ez.solve(xyinbit_ok, ez.XOR(xoutbit, youtbit));
if (is_edge)
satgen_db[inbit].insert(outbit);
if (verbose) {
bool is_ref_edge = edges_db.db.count(inbit) && edges_db.db.at(inbit).count(outbit);
log(" %c %s %s\n", is_edge ? 'x' : 'o', log_signal(outbit), is_edge == is_ref_edge ? "OK" : "ERROR");
}
}
}
if (satgen_db == edges_db.db)
log("PASS.\n");
else
log_error("SAT-based edge table does not match the database!\n");
}
static void run_eval_test(RTLIL::Design *design, bool verbose, bool nosat, std::string uut_name, std::ofstream &vlog_file)
{
log("Eval testing:%c", verbose ? '\n' : ' ');
@ -590,6 +675,9 @@ struct TestCellPass : public Pass {
log(" -noeval\n");
log(" do not check const-eval models\n");
log("\n");
log(" -edges\n");
log(" test cell edges db creator against sat-based implementation\n");
log("\n");
log(" -v\n");
log(" print additional debug information to the console\n");
log("\n");
@ -609,6 +697,7 @@ struct TestCellPass : public Pass {
bool constmode = false;
bool nosat = false;
bool noeval = false;
bool edges = false;
int argidx;
for (argidx = 1; argidx < GetSize(args); argidx++)
@ -662,6 +751,10 @@ struct TestCellPass : public Pass {
noeval = true;
continue;
}
if (args[argidx] == "-edges") {
edges = true;
continue;
}
if (args[argidx] == "-v") {
verbose = true;
continue;
@ -801,6 +894,9 @@ struct TestCellPass : public Pass {
create_gold_module(design, cell_type, cell_types.at(cell_type), constmode, muxdiv);
if (!write_prefix.empty()) {
Pass::call(design, stringf("write_ilang %s_%s_%05d.il", write_prefix.c_str(), cell_type.c_str()+1, i));
} else if (edges) {
Pass::call(design, "dump gold");
run_edges_test(design, verbose);
} else {
Pass::call(design, stringf("copy gold gate; cd gate; %s; cd ..; opt -fast gate", techmap_cmd.c_str()));
if (!nosat)