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Fix typo in manual 

Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2019-01-07 10:07:28 +01:00
parent 8a63fc51d3
commit f042559e9d
1 changed files with 1 additions and 1 deletions
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manual/CHAPTER_CellLib.tex
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@ -437,7 +437,7 @@ otherwise.
\begin{lstlisting}[mathescape,language=Verilog] \begin{lstlisting}[mathescape,language=Verilog]
always @($ClkEdge$ C, $RstEdge$ R) always @($ClkEdge$ C, $RstEdge$ R)
if (R == $RstLvl$) if (R == $RstLvl$)
Q <= $RstVa$l; Q <= $RstVal$;
else else
Q <= D; Q <= D;
\end{lstlisting} \end{lstlisting}