mirror of https://github.com/YosysHQ/yosys.git
Added SigMap::allbits()
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@ -421,6 +421,14 @@ struct SigMap
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apply(sig);
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return sig;
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}
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RTLIL::SigSpec allbits() const
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{
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RTLIL::SigSpec sig;
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for (auto &it : bits)
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sig.append(SigBit(it.first.first, it.first.second));
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return sig;
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}
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};
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YOSYS_NAMESPACE_END
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