mirror of https://github.com/YosysHQ/yosys.git
yosys-smtbmc --smtc -g
This commit is contained in:
Clifford Wolf
parent
cd18235f30
commit
ee3e7a0e45
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@ -58,7 +58,7 @@ yosys-smtbmc [options] <yosys_smt2_output>
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-m <module_name>
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name of the top module
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--constr <constr_filename>
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--smtc <constr_filename>
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read constraints file
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--dump-vcd <vcd_filename>
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@ -69,14 +69,14 @@ yosys-smtbmc [options] <yosys_smt2_output>
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--dump-vlogtb <verilog_filename>
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write trace as Verilog test bench
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--dump-constr <constr_filename>
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--dump-smtc <constr_filename>
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write trace as constraints file
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""" + so.helpmsg())
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sys.exit(1)
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try:
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opts, args = getopt.getopt(sys.argv[1:], so.shortopts + "t:u:S:igm:", so.longopts + ["constr=", "dump-vcd=", "dump-vlogtb=", "dump-constr="])
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opts, args = getopt.getopt(sys.argv[1:], so.shortopts + "t:u:S:igm:", so.longopts + ["smtc=", "dump-vcd=", "dump-vlogtb=", "dump-smtc="])
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except:
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usage()
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@ -92,13 +92,13 @@ for o, a in opts:
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assume_skipped = int(a)
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elif o == "-S":
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step_size = int(a)
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elif o == "--constr":
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elif o == "--smtc":
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inconstr.append(a)
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elif o == "--dump-vcd":
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vcdfile = a
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elif o == "--dump-vlogtb":
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vlogtbfile = a
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elif o == "--dump-constr":
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elif o == "--dump-smtc":
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outconstr = a
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elif o == "-i":
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tempind = True
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@ -116,7 +116,7 @@ if len(args) != 1:
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if tempind and len(inconstr) != 0:
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print("Error: options -i and --constr are exclusive.");
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print("Error: options -i and --smtc are exclusive.");
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sys.exit(1)
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@ -430,34 +430,6 @@ if tempind:
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break
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elif gentrace:
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retstatus = True
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for step in range(num_steps):
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smt.write("(declare-fun s%d () %s_s)" % (step, topmod))
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smt.write("(assert (%s_u s%d))" % (topmod, step))
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smt.write("(assert (%s_a s%d))" % (topmod, step))
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smt.write("(assert (%s_h s%d))" % (topmod, step))
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smt.write("(assert %s)" % get_constr_expr(constr_asserts, step))
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smt.write("(assert %s)" % get_constr_expr(constr_assumes, step))
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if step == 0:
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smt.write("(assert (%s_i s0))" % (topmod))
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smt.write("(assert (%s_is s0))" % (topmod))
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else:
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smt.write("(assert (%s_t s%d s%d))" % (topmod, step-1, step))
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smt.write("(assert (not (%s_is s%d)))" % (topmod, step))
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print("%s Creating trace of length %d.." % (smt.timestamp(), num_steps))
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if smt.check_sat() == "sat":
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write_trace(num_steps)
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else:
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print("%s Creating trace failed!" % smt.timestamp())
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retstatus = False
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else: # not tempind, not gentrace
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step = 0
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retstatus = True
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@ -495,30 +467,41 @@ else: # not tempind, not gentrace
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smt.write("(assert %s)" % get_constr_expr(constr_assumes, step+i))
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last_check_step = step+i
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if last_check_step == step:
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print("%s Checking asserts in step %d.." % (smt.timestamp(), step))
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else:
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print("%s Checking asserts in steps %d to %d.." % (smt.timestamp(), step, last_check_step))
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smt.write("(push 1)")
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if not gentrace:
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if last_check_step == step:
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print("%s Checking asserts in step %d.." % (smt.timestamp(), step))
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else:
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print("%s Checking asserts in steps %d to %d.." % (smt.timestamp(), step, last_check_step))
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smt.write("(push 1)")
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smt.write("(assert (not (and %s)))" % " ".join(["(%s_a s%d)" % (topmod, i) for i in range(step, last_check_step+1)] +
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[get_constr_expr(constr_asserts, i) for i in range(step, last_check_step+1)]))
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smt.write("(assert (not (and %s)))" % " ".join(["(%s_a s%d)" % (topmod, i) for i in range(step, last_check_step+1)] +
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[get_constr_expr(constr_asserts, i) for i in range(step, last_check_step+1)]))
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if smt.check_sat() == "sat":
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print("%s BMC failed!" % smt.timestamp())
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print_failed_asserts(topmod, "s%d" % step, topmod)
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write_trace(step+step_size)
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retstatus = False
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break
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if smt.check_sat() == "sat":
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print("%s BMC failed!" % smt.timestamp())
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print_failed_asserts(topmod, "s%d" % step, topmod)
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write_trace(step+step_size)
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retstatus = False
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break
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else: # unsat
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smt.write("(pop 1)")
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for i in range(step, last_check_step+1):
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smt.write("(assert (%s_a s%d))" % (topmod, i))
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smt.write("(assert %s)" % get_constr_expr(constr_asserts, i))
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for i in range(step, last_check_step+1):
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smt.write("(assert (%s_a s%d))" % (topmod, i))
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smt.write("(assert %s)" % get_constr_expr(constr_asserts, i))
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if gentrace:
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print("%s Solving for step %d.." % (smt.timestamp(), step))
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if smt.check_sat() != "sat":
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print("%s No solution found!" % smt.timestamp())
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retstatus = False
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break
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step += step_size
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if gentrace:
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write_trace(num_steps)
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smt.write("(exit)")
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smt.wait()
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@ -0,0 +1,9 @@
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demo1.smt2
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demo1.yslog
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demo2.smt2
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demo2.vcd
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demo2.yslog
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demo2_tb
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demo2_tb.smtc
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demo2_tb.v
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demo2_tb.vcd
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@ -6,19 +6,19 @@ demo1: demo1.smt2
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yosys-smtbmc -i --dump-vcd demo1.vcd demo1.smt2
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demo2: demo2.smt2
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yosys-smtbmc -g --dump-vcd demo2.vcd --dump-vlogtb demo2_tb.v --dump-constr demo2.smtc demo2.smt2
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yosys-smtbmc -g --dump-vcd demo2.vcd --dump-vlogtb demo2_tb.v --dump-smtc demo2_tb.smtc demo2.smt2
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iverilog -g2012 -o demo2_tb demo2_tb.v demo2.v
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vvp demo2_tb +vcd=demo2_tb.vcd
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demo1.smt2: demo1.v
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yosys -p 'read_verilog -formal demo1.v; prep -top demo1 -nordff; write_smt2 -wires -mem -bv demo1.smt2'
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yosys -ql demo1.yslog -p 'read_verilog -formal demo1.v; prep -top demo1 -nordff; write_smt2 -wires -mem -bv demo1.smt2'
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demo2.smt2: demo2.v
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yosys -p 'read_verilog -formal demo2.v; prep -top demo2 -nordff; write_smt2 -wires -mem -bv demo2.smt2'
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yosys -ql demo2.yslog -p 'read_verilog -formal demo2.v; prep -top demo2 -nordff; write_smt2 -wires -mem -bv demo2.smt2'
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clean:
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rm -f demo1.smt2 demo1.vcd
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rm -f demo2.smt2 demo2.vcd demo2_tb.v demo2_tb demo2_tb.vcd
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rm -f demo1.yslog demo1.smt2 demo1.vcd
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rm -f demo2.yslog demo2.smt2 demo2.vcd demo2_tb.v demo2_tb demo2_tb.vcd demo2_tb.smtc
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.PHONY: demo1 clean
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