mirror of https://github.com/YosysHQ/yosys.git
Merge remote-tracking branch 'origin/eddie/muxpack' into xc7mux
This commit is contained in:
Eddie Hung
commit
eaee250a6e
|
|
@ -16,6 +16,7 @@ Yosys 0.8 .. Yosys 0.8-dev
|
|||
- Added "gate2lut.v" techmap rule
|
||||
- Added "rename -src"
|
||||
- Added "equiv_opt" pass
|
||||
- Added "muxpack" pass
|
||||
- "synth_xilinx" to now infer hard shift registers, using new "shregmap -tech xilinx"
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -1532,27 +1532,31 @@ cell_port_list_rules:
|
|||
cell_port | cell_port_list_rules ',' cell_port;
|
||||
|
||||
cell_port:
|
||||
/* empty */ {
|
||||
attr {
|
||||
AstNode *node = new AstNode(AST_ARGUMENT);
|
||||
astbuf2->children.push_back(node);
|
||||
free_attr($1);
|
||||
} |
|
||||
expr {
|
||||
attr expr {
|
||||
AstNode *node = new AstNode(AST_ARGUMENT);
|
||||
astbuf2->children.push_back(node);
|
||||
node->children.push_back($1);
|
||||
node->children.push_back($2);
|
||||
free_attr($1);
|
||||
} |
|
||||
'.' TOK_ID '(' expr ')' {
|
||||
attr '.' TOK_ID '(' expr ')' {
|
||||
AstNode *node = new AstNode(AST_ARGUMENT);
|
||||
node->str = *$2;
|
||||
node->str = *$3;
|
||||
astbuf2->children.push_back(node);
|
||||
node->children.push_back($4);
|
||||
delete $2;
|
||||
node->children.push_back($5);
|
||||
delete $3;
|
||||
free_attr($1);
|
||||
} |
|
||||
'.' TOK_ID '(' ')' {
|
||||
attr '.' TOK_ID '(' ')' {
|
||||
AstNode *node = new AstNode(AST_ARGUMENT);
|
||||
node->str = *$2;
|
||||
node->str = *$3;
|
||||
astbuf2->children.push_back(node);
|
||||
delete $2;
|
||||
delete $3;
|
||||
free_attr($1);
|
||||
};
|
||||
|
||||
always_stmt:
|
||||
|
|
|
|||
|
|
@ -14,5 +14,6 @@ OBJS += passes/opt/opt_demorgan.o
|
|||
OBJS += passes/opt/rmports.o
|
||||
OBJS += passes/opt/opt_lut.o
|
||||
OBJS += passes/opt/pmux2shiftx.o
|
||||
OBJS += passes/opt/muxpack.o
|
||||
endif
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,266 @@
|
|||
/*
|
||||
* yosys -- Yosys Open SYnthesis Suite
|
||||
*
|
||||
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
|
||||
* 2019 Eddie Hung <eddie@fpgeh.com>
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#include "kernel/yosys.h"
|
||||
#include "kernel/sigtools.h"
|
||||
|
||||
USING_YOSYS_NAMESPACE
|
||||
PRIVATE_NAMESPACE_BEGIN
|
||||
|
||||
struct MuxpackWorker
|
||||
{
|
||||
Module *module;
|
||||
SigMap sigmap;
|
||||
|
||||
int mux_count, pmux_count;
|
||||
|
||||
pool<Cell*> remove_cells;
|
||||
|
||||
dict<SigSpec, Cell*> sig_chain_next;
|
||||
dict<SigSpec, Cell*> sig_chain_prev;
|
||||
pool<SigBit> sigbit_with_non_chain_users;
|
||||
pool<Cell*> chain_start_cells;
|
||||
pool<Cell*> candidate_cells;
|
||||
|
||||
void make_sig_chain_next_prev()
|
||||
{
|
||||
for (auto wire : module->wires())
|
||||
{
|
||||
if (wire->port_output || wire->get_bool_attribute("\\keep")) {
|
||||
for (auto bit : sigmap(wire))
|
||||
sigbit_with_non_chain_users.insert(bit);
|
||||
}
|
||||
}
|
||||
|
||||
for (auto cell : module->cells())
|
||||
{
|
||||
if (cell->type.in("$mux", "$pmux") && !cell->get_bool_attribute("\\keep"))
|
||||
{
|
||||
SigSpec a_sig = sigmap(cell->getPort("\\A"));
|
||||
SigSpec b_sig;
|
||||
if (cell->type == "$mux")
|
||||
b_sig = sigmap(cell->getPort("\\B"));
|
||||
SigSpec y_sig = sigmap(cell->getPort("\\Y"));
|
||||
|
||||
if (sig_chain_next.count(a_sig))
|
||||
for (auto a_bit : a_sig.bits())
|
||||
sigbit_with_non_chain_users.insert(a_bit);
|
||||
else {
|
||||
sig_chain_next[a_sig] = cell;
|
||||
candidate_cells.insert(cell);
|
||||
}
|
||||
|
||||
if (!b_sig.empty()) {
|
||||
if (sig_chain_next.count(b_sig))
|
||||
for (auto b_bit : b_sig.bits())
|
||||
sigbit_with_non_chain_users.insert(b_bit);
|
||||
else {
|
||||
sig_chain_next[b_sig] = cell;
|
||||
candidate_cells.insert(cell);
|
||||
}
|
||||
}
|
||||
|
||||
sig_chain_prev[y_sig] = cell;
|
||||
continue;
|
||||
}
|
||||
|
||||
for (auto conn : cell->connections())
|
||||
if (cell->input(conn.first))
|
||||
for (auto bit : sigmap(conn.second))
|
||||
sigbit_with_non_chain_users.insert(bit);
|
||||
}
|
||||
}
|
||||
|
||||
void find_chain_start_cells()
|
||||
{
|
||||
for (auto cell : candidate_cells)
|
||||
{
|
||||
log_debug("Considering %s (%s)\n", log_id(cell), log_id(cell->type));
|
||||
|
||||
SigSpec next_sig = cell->getPort("\\A");
|
||||
if (sig_chain_prev.count(next_sig) == 0) {
|
||||
if (cell->type == "$mux") {
|
||||
next_sig = cell->getPort("\\B");
|
||||
if (sig_chain_prev.count(next_sig) == 0)
|
||||
goto start_cell;
|
||||
}
|
||||
else
|
||||
goto start_cell;
|
||||
}
|
||||
|
||||
{
|
||||
for (auto bit : next_sig.bits())
|
||||
if (sigbit_with_non_chain_users.count(bit))
|
||||
goto start_cell;
|
||||
|
||||
Cell *c1 = sig_chain_prev.at(next_sig);
|
||||
Cell *c2 = cell;
|
||||
|
||||
if (c1->getParam("\\WIDTH") != c2->getParam("\\WIDTH"))
|
||||
goto start_cell;
|
||||
}
|
||||
|
||||
continue;
|
||||
|
||||
start_cell:
|
||||
chain_start_cells.insert(cell);
|
||||
}
|
||||
}
|
||||
|
||||
vector<Cell*> create_chain(Cell *start_cell)
|
||||
{
|
||||
vector<Cell*> chain;
|
||||
|
||||
Cell *c = start_cell;
|
||||
while (c != nullptr)
|
||||
{
|
||||
chain.push_back(c);
|
||||
|
||||
SigSpec y_sig = sigmap(c->getPort("\\Y"));
|
||||
|
||||
if (sig_chain_next.count(y_sig) == 0)
|
||||
break;
|
||||
|
||||
c = sig_chain_next.at(y_sig);
|
||||
if (chain_start_cells.count(c) != 0)
|
||||
break;
|
||||
}
|
||||
|
||||
return chain;
|
||||
}
|
||||
|
||||
void process_chain(vector<Cell*> &chain)
|
||||
{
|
||||
if (GetSize(chain) < 2)
|
||||
return;
|
||||
|
||||
int cursor = 0;
|
||||
while (cursor < GetSize(chain))
|
||||
{
|
||||
int cases = GetSize(chain) - cursor;
|
||||
|
||||
Cell *first_cell = chain[cursor];
|
||||
dict<int, SigBit> taps_dict;
|
||||
|
||||
if (cases < 2) {
|
||||
cursor++;
|
||||
continue;
|
||||
}
|
||||
|
||||
Cell *last_cell = chain[cursor+cases-1];
|
||||
|
||||
log("Converting %s.%s ... %s.%s to a pmux with %d cases.\n",
|
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log_id(module), log_id(first_cell), log_id(module), log_id(last_cell), cases);
|
||||
|
||||
mux_count += cases;
|
||||
pmux_count += 1;
|
||||
|
||||
first_cell->type = "$pmux";
|
||||
SigSpec b_sig = first_cell->getPort("\\B");
|
||||
SigSpec s_sig = first_cell->getPort("\\S");
|
||||
|
||||
for (int i = 1; i < cases; i++) {
|
||||
Cell* prev_cell = chain[cursor+i-1];
|
||||
Cell* cursor_cell = chain[cursor+i];
|
||||
if (sigmap(prev_cell->getPort("\\Y")) == sigmap(cursor_cell->getPort("\\A"))) {
|
||||
b_sig.append(cursor_cell->getPort("\\B"));
|
||||
s_sig.append(cursor_cell->getPort("\\S"));
|
||||
}
|
||||
else {
|
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b_sig.append(cursor_cell->getPort("\\A"));
|
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s_sig.append(module->LogicNot(NEW_ID, cursor_cell->getPort("\\S")));
|
||||
}
|
||||
remove_cells.insert(cursor_cell);
|
||||
}
|
||||
|
||||
first_cell->setPort("\\B", b_sig);
|
||||
first_cell->setPort("\\S", s_sig);
|
||||
first_cell->setParam("\\S_WIDTH", GetSize(s_sig));
|
||||
first_cell->setPort("\\Y", last_cell->getPort("\\Y"));
|
||||
|
||||
cursor += cases;
|
||||
}
|
||||
}
|
||||
|
||||
void cleanup()
|
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{
|
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for (auto cell : remove_cells)
|
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module->remove(cell);
|
||||
|
||||
remove_cells.clear();
|
||||
sig_chain_next.clear();
|
||||
sig_chain_prev.clear();
|
||||
chain_start_cells.clear();
|
||||
candidate_cells.clear();
|
||||
}
|
||||
|
||||
MuxpackWorker(Module *module) :
|
||||
module(module), sigmap(module), mux_count(0), pmux_count(0)
|
||||
{
|
||||
make_sig_chain_next_prev();
|
||||
find_chain_start_cells();
|
||||
|
||||
for (auto c : chain_start_cells) {
|
||||
vector<Cell*> chain = create_chain(c);
|
||||
process_chain(chain);
|
||||
}
|
||||
|
||||
cleanup();
|
||||
}
|
||||
};
|
||||
|
||||
struct MuxpackPass : public Pass {
|
||||
MuxpackPass() : Pass("muxpack", "$mux/$pmux cascades to $pmux") { }
|
||||
void help() YS_OVERRIDE
|
||||
{
|
||||
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
|
||||
log("\n");
|
||||
log(" muxpack [selection]\n");
|
||||
log("\n");
|
||||
log("This pass converts cascaded chains of $pmux cells (e.g. those create from case\n");
|
||||
log("constructs) and $mux cells (e.g. those created by if-else constructs) into \n");
|
||||
log("into $pmux cells.\n");
|
||||
log("\n");
|
||||
}
|
||||
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
|
||||
{
|
||||
log_header(design, "Executing MUXPACK pass ($mux cell cascades to $pmux).\n");
|
||||
|
||||
size_t argidx;
|
||||
for (argidx = 1; argidx < args.size(); argidx++)
|
||||
{
|
||||
break;
|
||||
}
|
||||
extra_args(args, argidx, design);
|
||||
|
||||
int mux_count = 0;
|
||||
int pmux_count = 0;
|
||||
|
||||
for (auto module : design->selected_modules()) {
|
||||
MuxpackWorker worker(module);
|
||||
mux_count += worker.mux_count;
|
||||
pmux_count += worker.pmux_count;
|
||||
}
|
||||
|
||||
log("Converted %d (p)mux cells into %d pmux cells.\n", mux_count, pmux_count);
|
||||
}
|
||||
} MuxpackPass;
|
||||
|
||||
PRIVATE_NAMESPACE_END
|
||||
|
|
@ -292,8 +292,8 @@ bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff)
|
|||
sig_q = dff->getPort("\\Q");
|
||||
sig_c = dff->getPort("\\C");
|
||||
sig_e = dff->getPort("\\E");
|
||||
val_cp = RTLIL::Const(dff->type[6] == 'P', 1);
|
||||
val_ep = RTLIL::Const(dff->type[7] == 'P', 1);
|
||||
val_cp = RTLIL::Const(dff->type[7] == 'P', 1);
|
||||
val_ep = RTLIL::Const(dff->type[8] == 'P', 1);
|
||||
}
|
||||
else if (dff->type == "$ff") {
|
||||
sig_d = dff->getPort("\\D");
|
||||
|
|
|
|||
|
|
@ -88,6 +88,8 @@ struct SimInstance
|
|||
SimInstance(SimShared *shared, Module *module, Cell *instance = nullptr, SimInstance *parent = nullptr) :
|
||||
shared(shared), module(module), instance(instance), parent(parent), sigmap(module)
|
||||
{
|
||||
log_assert(module);
|
||||
|
||||
if (parent) {
|
||||
log_assert(parent->children.count(instance) == 0);
|
||||
parent->children[instance] = this;
|
||||
|
|
@ -848,6 +850,9 @@ struct SimPass : public Pass {
|
|||
|
||||
if (design->full_selection()) {
|
||||
top_mod = design->top_module();
|
||||
|
||||
if (!top_mod)
|
||||
log_cmd_error("Design has no top module, use the 'hierarchy' command to specify one.\n");
|
||||
} else {
|
||||
auto mods = design->selected_whole_modules();
|
||||
if (GetSize(mods) != 1)
|
||||
|
|
|
|||
|
|
@ -723,6 +723,9 @@ struct ShregmapPass : public Pass {
|
|||
log(" -tech greenpak4\n");
|
||||
log(" map to greenpak4 shift registers.\n");
|
||||
log("\n");
|
||||
log(" -tech xilinx\n");
|
||||
log(" map to xilinx dynamic-length shift registers.\n");
|
||||
log("\n");
|
||||
}
|
||||
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
|
||||
{
|
||||
|
|
|
|||
|
|
@ -47,6 +47,21 @@ module \$__DFFSE_NP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"
|
|||
module \$__DFFSE_PP0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
|
||||
module \$__DFFSE_PP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
|
||||
|
||||
// Diamond I/O buffers
|
||||
module IB (input I, output O); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("INPUT")) _TECHMAP_REPLACE_ (.B(I), .O(O)); endmodule
|
||||
module IBPU (input I, output O); (* PULLMODE="UP" *) TRELLIS_IO #(.DIR("INPUT")) _TECHMAP_REPLACE_ (.B(I), .O(O)); endmodule
|
||||
module IBPD (input I, output O); (* PULLMODE="DOWN" *) TRELLIS_IO #(.DIR("INPUT")) _TECHMAP_REPLACE_ (.B(I), .O(O)); endmodule
|
||||
module OB (input I, output O); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(O), .I(I)); endmodule
|
||||
module OBZ (input I, T, output O); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(O), .I(I), .T(T)); endmodule
|
||||
module OBZPU(input I, T, output O); (* PULLMODE="UP" *) TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(O), .I(I), .T(T)); endmodule
|
||||
module OBZPD(input I, T, output O); (* PULLMODE="DOWN" *) TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(O), .I(I), .T(T)); endmodule
|
||||
module OBCO (input I, output OT, OC); OLVDS _TECHMAP_REPLACE_ (.A(I), .Z(OT), .ZN(OC)); endmodule
|
||||
module BB (input I, T, output O, inout B); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("BIDIR")) _TECHMAP_REPLACE_ (.B(B), .I(I), .O(O), .T(T)); endmodule
|
||||
module BBPU (input I, T, output O, inout B); (* PULLMODE="UP" *) TRELLIS_IO #(.DIR("BIDIR")) _TECHMAP_REPLACE_ (.B(B), .I(I), .O(O), .T(T)); endmodule
|
||||
module BBPD (input I, T, output O, inout B); (* PULLMODE="DOWN" *) TRELLIS_IO #(.DIR("BIDIR")) _TECHMAP_REPLACE_ (.B(B), .I(I), .O(O), .T(T)); endmodule
|
||||
module ILVDS(input A, AN, output Z); TRELLIS_IO #(.DIR("INPUT")) _TECHMAP_REPLACE_ (.B(A), .O(Z)); endmodule
|
||||
module OLVDS(input A, output Z, ZN); TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(Z), .I(A)); endmodule
|
||||
|
||||
// For Diamond compatibility, FIXME: add all Diamond flipflop mappings
|
||||
module FD1S3BX(input PD, D, CK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(PD), .DI(D), .Q(Q)); endmodule
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,21 @@
|
|||
module bar(clk, rst, inp, out);
|
||||
input wire clk;
|
||||
input wire rst;
|
||||
input wire inp;
|
||||
output reg out;
|
||||
|
||||
always @(posedge clk)
|
||||
if (rst) out <= 1'd0;
|
||||
else out <= ~inp;
|
||||
|
||||
endmodule
|
||||
|
||||
module foo(clk, rst, inp, out);
|
||||
input wire clk;
|
||||
input wire rst;
|
||||
input wire inp;
|
||||
output wire out;
|
||||
|
||||
bar bar_instance (clk, rst, inp, out);
|
||||
endmodule
|
||||
|
||||
|
|
@ -0,0 +1,25 @@
|
|||
module bar(clk, rst, inp, out);
|
||||
(* this_is_clock = 1 *)
|
||||
input wire clk;
|
||||
(* this_is_reset = 1 *)
|
||||
input wire rst;
|
||||
input wire inp;
|
||||
(* an_output_register = 1*)
|
||||
output reg out;
|
||||
|
||||
always @(posedge clk)
|
||||
if (rst) out <= 1'd0;
|
||||
else out <= ~inp;
|
||||
|
||||
endmodule
|
||||
|
||||
module foo(clk, rst, inp, out);
|
||||
(* this_is_the_master_clock *)
|
||||
input wire clk;
|
||||
input wire rst;
|
||||
input wire inp;
|
||||
output wire out;
|
||||
|
||||
bar bar_instance (clk, rst, inp, out);
|
||||
endmodule
|
||||
|
||||
|
|
@ -0,0 +1,28 @@
|
|||
module bar(clk, rst, inp, out);
|
||||
|
||||
(* bus_width *)
|
||||
parameter WIDTH = 2;
|
||||
|
||||
(* an_attribute_on_localparam = 55 *)
|
||||
localparam INCREMENT = 5;
|
||||
|
||||
input wire clk;
|
||||
input wire rst;
|
||||
input wire [WIDTH-1:0] inp;
|
||||
output reg [WIDTH-1:0] out;
|
||||
|
||||
always @(posedge clk)
|
||||
if (rst) out <= 0;
|
||||
else out <= inp + INCREMENT;
|
||||
|
||||
endmodule
|
||||
|
||||
module foo(clk, rst, inp, out);
|
||||
input wire clk;
|
||||
input wire rst;
|
||||
input wire [7:0] inp;
|
||||
output wire [7:0] out;
|
||||
|
||||
bar # (.WIDTH(8)) bar_instance (clk, rst, inp, out);
|
||||
endmodule
|
||||
|
||||
|
|
@ -0,0 +1,32 @@
|
|||
module bar(clk, rst, inp, out);
|
||||
input wire clk;
|
||||
input wire rst;
|
||||
input wire inp;
|
||||
output reg out;
|
||||
|
||||
(* this_is_a_prescaler *)
|
||||
reg [7:0] counter;
|
||||
|
||||
(* temp_wire *)
|
||||
wire out_val;
|
||||
|
||||
always @(posedge clk)
|
||||
counter <= counter + 1;
|
||||
|
||||
assign out_val = inp ^ counter[4];
|
||||
|
||||
always @(posedge clk)
|
||||
if (rst) out <= 1'd0;
|
||||
else out <= out_val;
|
||||
|
||||
endmodule
|
||||
|
||||
module foo(clk, rst, inp, out);
|
||||
input wire clk;
|
||||
input wire rst;
|
||||
input wire inp;
|
||||
output wire out;
|
||||
|
||||
bar bar_instance (clk, rst, inp, out);
|
||||
endmodule
|
||||
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
module bar(clk, rst, inp, out);
|
||||
input wire clk;
|
||||
input wire rst;
|
||||
input wire inp;
|
||||
output reg out;
|
||||
|
||||
always @(posedge clk)
|
||||
if (rst) out <= 1'd0;
|
||||
else out <= ~inp;
|
||||
|
||||
endmodule
|
||||
|
||||
module foo(clk, rst, inp, out);
|
||||
input wire clk;
|
||||
input wire rst;
|
||||
input wire inp;
|
||||
output wire out;
|
||||
|
||||
bar bar_instance ( (* clock_connected *) clk, rst, (* this_is_the_input *) inp, out);
|
||||
endmodule
|
||||
|
||||
|
|
@ -0,0 +1,23 @@
|
|||
module bar(clk, rst, inp_a, inp_b, out);
|
||||
input wire clk;
|
||||
input wire rst;
|
||||
input wire [7:0] inp_a;
|
||||
input wire [7:0] inp_b;
|
||||
output reg [7:0] out;
|
||||
|
||||
always @(posedge clk)
|
||||
if (rst) out <= 0;
|
||||
else out <= inp_a + (* ripple_adder *) inp_b;
|
||||
|
||||
endmodule
|
||||
|
||||
module foo(clk, rst, inp_a, inp_b, out);
|
||||
input wire clk;
|
||||
input wire rst;
|
||||
input wire [7:0] inp_a;
|
||||
input wire [7:0] inp_b;
|
||||
output wire [7:0] out;
|
||||
|
||||
bar bar_instance (clk, rst, inp_a, inp_b, out);
|
||||
endmodule
|
||||
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
function [7:0] do_add;
|
||||
input [7:0] inp_a;
|
||||
input [7:0] inp_b;
|
||||
|
||||
do_add = inp_a + inp_b;
|
||||
|
||||
endfunction
|
||||
|
||||
module foo(clk, rst, inp_a, inp_b, out);
|
||||
input wire clk;
|
||||
input wire rst;
|
||||
input wire [7:0] inp_a;
|
||||
input wire [7:0] inp_b;
|
||||
output wire [7:0] out;
|
||||
|
||||
always @(posedge clk)
|
||||
if (rst) out <= 0;
|
||||
else out <= do_add (* combinational_adder *) (inp_a, inp_b);
|
||||
|
||||
endmodule
|
||||
|
||||
|
|
@ -0,0 +1,22 @@
|
|||
module bar(clk, rst, inp, out);
|
||||
input wire clk;
|
||||
input wire rst;
|
||||
input wire inp;
|
||||
output reg out;
|
||||
|
||||
always @(posedge clk)
|
||||
if (rst) out <= 1'd0;
|
||||
else out <= ~inp;
|
||||
|
||||
endmodule
|
||||
|
||||
module foo(clk, rst, inp, out);
|
||||
input wire clk;
|
||||
input wire rst;
|
||||
input wire inp;
|
||||
output wire out;
|
||||
|
||||
(* my_module_instance = 99 *)
|
||||
bar bar_instance (clk, rst, inp, out);
|
||||
endmodule
|
||||
|
||||
|
|
@ -0,0 +1,26 @@
|
|||
module bar(clk, rst, inp, out);
|
||||
input wire clk;
|
||||
input wire rst;
|
||||
input wire [1:0] inp;
|
||||
output reg [1:0] out;
|
||||
|
||||
always @(inp)
|
||||
(* full_case, parallel_case *)
|
||||
case(inp)
|
||||
2'd0: out <= 2'd3;
|
||||
2'd1: out <= 2'd2;
|
||||
2'd2: out <= 2'd1;
|
||||
2'd3: out <= 2'd0;
|
||||
endcase
|
||||
|
||||
endmodule
|
||||
|
||||
module foo(clk, rst, inp, out);
|
||||
input wire clk;
|
||||
input wire rst;
|
||||
input wire [1:0] inp;
|
||||
output wire [1:0] out;
|
||||
|
||||
bar bar_instance (clk, rst, inp, out);
|
||||
endmodule
|
||||
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
module bar(clk, rst, inp, out);
|
||||
input wire clk;
|
||||
input wire rst;
|
||||
input wire inp;
|
||||
output reg out;
|
||||
|
||||
always @(posedge clk)
|
||||
if (rst) out <= 1'd0;
|
||||
else out <= ~inp;
|
||||
|
||||
endmodule
|
||||
|
||||
module foo(clk, rst, inp, out);
|
||||
input wire clk;
|
||||
input wire rst;
|
||||
input wire inp;
|
||||
output wire out;
|
||||
|
||||
bar bar_instance ( (* clock_connected *) clk, rst, (* this_is_the_input *) inp, out);
|
||||
endmodule
|
||||
|
||||
|
|
@ -0,0 +1,2 @@
|
|||
# Read and parse Verilog file
|
||||
read_verilog attrib05_port_conn.v
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
function [7:0] do_add;
|
||||
input [7:0] inp_a;
|
||||
input [7:0] inp_b;
|
||||
|
||||
do_add = inp_a + inp_b;
|
||||
|
||||
endfunction
|
||||
|
||||
module foo(clk, rst, inp_a, inp_b, out);
|
||||
input wire clk;
|
||||
input wire rst;
|
||||
input wire [7:0] inp_a;
|
||||
input wire [7:0] inp_b;
|
||||
output wire [7:0] out;
|
||||
|
||||
always @(posedge clk)
|
||||
if (rst) out <= 0;
|
||||
else out <= do_add (* combinational_adder *) (inp_a, inp_b);
|
||||
|
||||
endmodule
|
||||
|
||||
|
|
@ -0,0 +1,2 @@
|
|||
# Read and parse Verilog file
|
||||
read_verilog attrib07_func_call.v
|
||||
|
|
@ -0,0 +1,112 @@
|
|||
module mux_if_unbal_4_1 #(parameter N=4, parameter W=1) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
|
||||
always @*
|
||||
if (s == 0) o <= i[0*W+:W];
|
||||
else if (s == 1) o <= i[1*W+:W];
|
||||
else if (s == 2) o <= i[2*W+:W];
|
||||
else if (s == 3) o <= i[3*W+:W];
|
||||
else o <= {W{1'bx}};
|
||||
endmodule
|
||||
|
||||
module mux_if_unbal_5_3 #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
|
||||
always @* begin
|
||||
o <= {W{1'bx}};
|
||||
if (s == 0) o <= i[0*W+:W];
|
||||
if (s == 1) o <= i[1*W+:W];
|
||||
if (s == 2) o <= i[2*W+:W];
|
||||
if (s == 3) o <= i[3*W+:W];
|
||||
if (s == 4) o <= i[4*W+:W];
|
||||
end
|
||||
endmodule
|
||||
|
||||
module mux_if_unbal_5_3_invert #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
|
||||
always @*
|
||||
if (s != 0)
|
||||
if (s != 1)
|
||||
if (s != 2)
|
||||
if (s != 3)
|
||||
if (s != 4) o <= i[4*W+:W];
|
||||
else o <= i[0*W+:W];
|
||||
else o <= i[3*W+:W];
|
||||
else o <= i[2*W+:W];
|
||||
else o <= i[1*W+:W];
|
||||
else o <= {W{1'bx}};
|
||||
endmodule
|
||||
|
||||
module mux_if_unbal_5_3_width_mismatch #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
|
||||
always @* begin
|
||||
o <= {W{1'bx}};
|
||||
if (s == 0) o <= i[0*W+:W];
|
||||
if (s == 1) o <= i[1*W+:W];
|
||||
if (s == 2) o[W-2:0] <= i[2*W+:W-1];
|
||||
if (s == 3) o <= i[3*W+:W];
|
||||
if (s == 4) o <= i[4*W+:W];
|
||||
end
|
||||
endmodule
|
||||
|
||||
module mux_if_unbal_4_1_missing #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
|
||||
always @* begin
|
||||
if (s == 0) o <= i[0*W+:W];
|
||||
// else if (s == 1) o <= i[1*W+:W];
|
||||
// else if (s == 2) o <= i[2*W+:W];
|
||||
else if (s == 3) o <= i[3*W+:W];
|
||||
else o <= {W{1'bx}};
|
||||
end
|
||||
endmodule
|
||||
|
||||
module mux_if_unbal_5_3_order #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
|
||||
always @* begin
|
||||
o <= {W{1'bx}};
|
||||
if (s == 3) o <= i[3*W+:W];
|
||||
if (s == 2) o <= i[2*W+:W];
|
||||
if (s == 1) o <= i[1*W+:W];
|
||||
if (s == 4) o <= i[4*W+:W];
|
||||
if (s == 0) o <= i[0*W+:W];
|
||||
end
|
||||
endmodule
|
||||
|
||||
module mux_if_unbal_4_1_nonexcl #(parameter N=4, parameter W=1) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
|
||||
always @*
|
||||
if (s == 0) o <= i[0*W+:W];
|
||||
else if (s == 1) o <= i[1*W+:W];
|
||||
else if (s == 2) o <= i[2*W+:W];
|
||||
else if (s == 3) o <= i[3*W+:W];
|
||||
else if (s == 0) o <= {W{1'b0}};
|
||||
else o <= {W{1'bx}};
|
||||
endmodule
|
||||
|
||||
module mux_if_unbal_5_3_nonexcl #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
|
||||
always @* begin
|
||||
o <= {W{1'bx}};
|
||||
if (s == 0) o <= i[0*W+:W];
|
||||
if (s == 1) o <= i[1*W+:W];
|
||||
if (s == 2) o <= i[2*W+:W];
|
||||
if (s == 3) o <= i[3*W+:W];
|
||||
if (s == 4) o <= i[4*W+:W];
|
||||
if (s == 0) o <= i[2*W+:W];
|
||||
end
|
||||
endmodule
|
||||
|
||||
module mux_case_unbal_8_7#(parameter N=8, parameter W=7) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
|
||||
always @* begin
|
||||
o <= {W{1'bx}};
|
||||
case (s)
|
||||
0: o <= i[0*W+:W];
|
||||
default:
|
||||
case (s)
|
||||
1: o <= i[1*W+:W];
|
||||
2: o <= i[2*W+:W];
|
||||
default:
|
||||
case (s)
|
||||
3: o <= i[3*W+:W];
|
||||
4: o <= i[4*W+:W];
|
||||
5: o <= i[5*W+:W];
|
||||
default:
|
||||
case (s)
|
||||
6: o <= i[6*W+:W];
|
||||
default: o <= i[7*W+:W];
|
||||
endcase
|
||||
endcase
|
||||
endcase
|
||||
endcase
|
||||
end
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,135 @@
|
|||
read_verilog muxpack.v
|
||||
design -save read
|
||||
hierarchy -top mux_if_unbal_4_1
|
||||
prep
|
||||
design -save gold
|
||||
muxpack
|
||||
opt
|
||||
stat
|
||||
select -assert-count 0 t:$mux
|
||||
select -assert-count 1 t:$pmux
|
||||
design -stash gate
|
||||
design -import gold -as gold
|
||||
design -import gate -as gate
|
||||
miter -equiv -flatten -make_assert -make_outputs gold gate miter
|
||||
sat -verify -prove-asserts -show-ports miter
|
||||
|
||||
design -load read
|
||||
hierarchy -top mux_if_unbal_5_3
|
||||
prep
|
||||
design -save gold
|
||||
muxpack
|
||||
opt
|
||||
stat
|
||||
select -assert-count 0 t:$mux
|
||||
select -assert-count 1 t:$pmux
|
||||
design -stash gate
|
||||
design -import gold -as gold
|
||||
design -import gate -as gate
|
||||
miter -equiv -flatten -make_assert -make_outputs gold gate miter
|
||||
sat -verify -prove-asserts -show-ports miter
|
||||
|
||||
design -load read
|
||||
hierarchy -top mux_if_unbal_5_3_invert
|
||||
prep
|
||||
design -save gold
|
||||
muxpack
|
||||
opt
|
||||
stat
|
||||
select -assert-count 0 t:$mux
|
||||
select -assert-count 1 t:$pmux
|
||||
design -stash gate
|
||||
design -import gold -as gold
|
||||
design -import gate -as gate
|
||||
miter -equiv -flatten -make_assert -make_outputs gold gate miter
|
||||
sat -verify -prove-asserts -show-ports miter
|
||||
|
||||
design -load read
|
||||
hierarchy -top mux_if_unbal_5_3_width_mismatch
|
||||
prep
|
||||
design -save gold
|
||||
muxpack
|
||||
opt
|
||||
stat
|
||||
select -assert-count 0 t:$mux
|
||||
select -assert-count 2 t:$pmux
|
||||
design -stash gate
|
||||
design -import gold -as gold
|
||||
design -import gate -as gate
|
||||
miter -equiv -flatten -make_assert -make_outputs gold gate miter
|
||||
sat -verify -prove-asserts -show-ports miter
|
||||
|
||||
design -load read
|
||||
hierarchy -top mux_if_unbal_4_1_missing
|
||||
prep
|
||||
design -save gold
|
||||
muxpack
|
||||
opt
|
||||
stat
|
||||
select -assert-count 0 t:$mux
|
||||
select -assert-count 1 t:$pmux
|
||||
design -stash gate
|
||||
design -import gold -as gold
|
||||
design -import gate -as gate
|
||||
miter -equiv -flatten -make_assert -make_outputs gold gate miter
|
||||
sat -verify -prove-asserts -show-ports miter
|
||||
|
||||
design -load read
|
||||
hierarchy -top mux_if_unbal_5_3_order
|
||||
prep
|
||||
design -save gold
|
||||
muxpack
|
||||
opt
|
||||
stat
|
||||
select -assert-count 0 t:$mux
|
||||
select -assert-count 1 t:$pmux
|
||||
design -stash gate
|
||||
design -import gold -as gold
|
||||
design -import gate -as gate
|
||||
miter -equiv -flatten -make_assert -make_outputs gold gate miter
|
||||
sat -verify -prove-asserts -show-ports miter
|
||||
|
||||
design -load read
|
||||
hierarchy -top mux_if_unbal_4_1_nonexcl
|
||||
prep
|
||||
design -save gold
|
||||
muxpack
|
||||
opt
|
||||
stat
|
||||
select -assert-count 0 t:$mux
|
||||
select -assert-count 1 t:$pmux
|
||||
design -stash gate
|
||||
design -import gold -as gold
|
||||
design -import gate -as gate
|
||||
miter -equiv -flatten -make_assert -make_outputs gold gate miter
|
||||
sat -verify -prove-asserts -show-ports miter
|
||||
|
||||
design -load read
|
||||
hierarchy -top mux_if_unbal_5_3_nonexcl
|
||||
prep
|
||||
design -save gold
|
||||
muxpack
|
||||
opt
|
||||
stat
|
||||
select -assert-count 0 t:$mux
|
||||
select -assert-count 1 t:$pmux
|
||||
design -stash gate
|
||||
design -import gold -as gold
|
||||
design -import gate -as gate
|
||||
miter -equiv -flatten -make_assert -make_outputs gold gate miter
|
||||
sat -verify -prove-asserts -show-ports miter
|
||||
|
||||
design -load read
|
||||
hierarchy -top mux_case_unbal_8_7
|
||||
prep
|
||||
design -save gold
|
||||
muxpack
|
||||
opt
|
||||
stat
|
||||
select -assert-count 0 t:$mux
|
||||
select -assert-count 1 t:$pmux
|
||||
design -stash gate
|
||||
design -import gold -as gold
|
||||
design -import gate -as gate
|
||||
miter -equiv -flatten -make_assert -make_outputs gold gate miter
|
||||
sat -verify -prove-asserts -show-ports miter
|
||||
Loading…
Reference in New Issue