mirror of https://github.com/YosysHQ/yosys.git
Fixed another bug found using vloghammer
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@ -798,7 +798,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint)
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if (0) { case AST_SHIFT_SLEFT: type_name = "$sshl"; is_signed = true; }
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if (0) { case AST_SHIFT_SLEFT: type_name = "$sshl"; is_signed = true; }
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if (0) { case AST_SHIFT_SRIGHT: type_name = "$sshr"; is_signed = true; }
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if (0) { case AST_SHIFT_SRIGHT: type_name = "$sshr"; is_signed = true; }
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{
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{
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RTLIL::SigSpec left = children[0]->genRTLIL(width_hint);
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RTLIL::SigSpec left = children[0]->genRTLIL();
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RTLIL::SigSpec right = children[1]->genRTLIL(width_hint);
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RTLIL::SigSpec right = children[1]->genRTLIL(width_hint);
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int width = width_hint > 0 ? width_hint : left.width;
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int width = width_hint > 0 ? width_hint : left.width;
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return binop2rtlil(this, type_name, width, left, right);
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return binop2rtlil(this, type_name, width, left, right);
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@ -0,0 +1,10 @@
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// test cases found using vloghammer
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// https://github.com/cliffordwolf/VlogHammer
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module test01(a, y);
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input [7:0] a;
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output [3:0] y;
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assign y = ~a >> 4;
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endmodule
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