Update macc test

tests/xilinx/macc.v

@@ -1,37 +1,41 @@
 // Signed 40-bit streaming accumulator with 16-bit inputs
 // File: HDL_Coding_Techniques/multipliers/multipliers4.v
 //
-module macc # (parameter SIZEIN = /*16*/7, SIZEOUT = 40)
+// Source:
- (input clk, ce, sload,
+// https://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_2/ug901-vivado-synthesis.pdf p.90
- input signed [SIZEIN-1:0] a, b,
+//
- output signed [SIZEOUT-1:0] accum_out);
+module macc # (parameter SIZEIN = 16, SIZEOUT = 40) (
- // Declare registers for intermediate values
+	input clk, ce, sload,
- reg signed [SIZEIN-1:0] a_reg, b_reg;
+	input signed [SIZEIN-1:0] a, b,
- reg sload_reg;
+	output signed [SIZEOUT-1:0] accum_out
- reg signed [2*SIZEIN:0] mult_reg;
+);
- reg signed [SIZEOUT-1:0] adder_out, old_result;
+// Declare registers for intermediate values
- always @(adder_out or sload_reg) begin
+reg signed [SIZEIN-1:0] a_reg, b_reg;
- //if (sload_reg)
+reg sload_reg;
- //old_result <= 0;
+reg signed [2*SIZEIN-1:0] mult_reg;
- //else
+reg signed [SIZEOUT-1:0] adder_out, old_result;
- // 'sload' is now active (=low) and opens the accumulation loop.
+always @* /*(adder_out or sload_reg)*/ begin // Modification necessary to fix sim/synth mismatch
- // The accumulator takes the next multiplier output in
+	if (sload_reg)
- // the same cycle.
+		old_result <= 0;
- old_result <= adder_out;
+	else
- a_reg <= a;
+		// 'sload' is now active (=low) and opens the accumulation loop.
- b_reg <= b;
+		// The accumulator takes the next multiplier output in
- end
+		// the same cycle.
+		old_result <= adder_out;
+end
 
- always @(posedge clk)
+always @(posedge clk)
- //if (ce)
+	if (ce)
- begin
+	begin
- mult_reg <= a_reg * b_reg;
+		a_reg <= a;
- sload_reg <= sload;
+		b_reg <= b;
- // Store accumulation result into a register
+		mult_reg <= a_reg * b_reg;
- adder_out <= old_result + mult_reg;
+		sload_reg <= sload;
- end
+		// Store accumulation result into a register
+		adder_out <= old_result + mult_reg;
+	end
 
- // Output accumulation result
+	// Output accumulation result
- assign accum_out = adder_out;
+	assign accum_out = adder_out;
 
-endmodule // macc
+endmodule

tests/xilinx/macc.ys

@@ -1,17 +1,13 @@
 read_verilog macc.v
 proc
-hierarchy -top macc
+hierarchy -auto-top
-equiv_opt -run :restore -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+#equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx ### TODO
-
+equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
-#equiv_miter -trigger miter equiv
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
-#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
+sat -verify -prove-asserts -seq 10 -show-inputs -show-outputs miter
-
-#equiv_opt -assert -run :prove -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
-#miter -equiv -flatten -make_assert -make_outputs gold gate miter
-#sat -set-init-zero -verify -prove-asserts -seq 10 -show-inputs -show-outputs miter
-
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd macc # Constrain all select calls below inside the top module
 select -assert-count 1 t:BUFG
+select -assert-count 1 t:FDRE
 select -assert-count 1 t:DSP48E1
-select -assert-none t:BUFG t:DSP48E1 %% t:* %D
+select -assert-none t:BUFG t:FDRE t:DSP48E1 %% t:* %D