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Cope with sign extension in mul2dsp

This commit is contained in:
Eddie Hung 2019-08-01 12:44:56 -07:00
parent 332b86491d
commit e19d33b003
2 changed files with 14 additions and 14 deletions
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16
passes/pmgen/ice40_dsp.cc
View File

@ -72,17 +72,17 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
pm.module->swap_names(cell, st.mul); pm.module->swap_names(cell, st.mul);
// SB_MAC16 Input Interface // SB_MAC16 Input Interface
bool a_signed = st.mul->getParam("\\A_SIGNED").as_bool();
bool b_signed = st.mul->getParam("\\B_SIGNED").as_bool();
SigSpec A = st.sigA; SigSpec A = st.sigA;
A.extend_u0(16, a_signed); log_assert(GetSize(A) == 16);
SigSpec B = st.sigB; SigSpec B = st.sigB;
B.extend_u0(16, b_signed); log_assert(GetSize(B) == 16);
SigSpec CD = st.sigCD; SigSpec CD = st.sigCD;
CD.extend_u0(32, st.sigCD_signed); if (CD.empty())
CD = RTLIL::Const(0, 32);
else
log_assert(GetSize(CD) == 32);
cell->setPort("\\A", A); cell->setPort("\\A", A);
cell->setPort("\\B", B); cell->setPort("\\B", B);
@ -217,8 +217,8 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
cell->setParam("\\BOTADDSUB_CARRYSELECT", Const(0, 2)); cell->setParam("\\BOTADDSUB_CARRYSELECT", Const(0, 2));
cell->setParam("\\MODE_8x8", State::S0); cell->setParam("\\MODE_8x8", State::S0);
cell->setParam("\\A_SIGNED", a_signed); cell->setParam("\\A_SIGNED", st.mul->getParam("\\A_SIGNED").as_bool());
cell->setParam("\\B_SIGNED", b_signed); cell->setParam("\\B_SIGNED", st.mul->getParam("\\B_SIGNED").as_bool());
pm.autoremove(st.mul); pm.autoremove(st.mul);
pm.autoremove(st.ffH); pm.autoremove(st.ffH);

12
passes/pmgen/ice40_dsp.pmg
View File

@ -1,7 +1,7 @@
pattern ice40_dsp pattern ice40_dsp
state <SigBit> clock state <SigBit> clock
state <bool> clock_pol sigCD_signed state <bool> clock_pol
state <SigSpec> sigA sigB sigCD sigH sigO state <SigSpec> sigA sigB sigCD sigH sigO
state <Cell*> addAB muxAB state <Cell*> addAB muxAB
@ -94,16 +94,16 @@ match addB
optional optional
endmatch endmatch
code addAB sigCD sigCD_signed sigO code addAB sigCD sigO
if (addA) { if (addA) {
addAB = addA; addAB = addA;
sigCD = port(addAB, \B); sigCD = port(addAB, \B);
sigCD_signed = param(addAB, \B_SIGNED).as_bool(); sigCD.extend_u0(32, param(addAB, \B_SIGNED).as_bool());
} }
if (addB) { if (addB) {
addAB = addB; addAB = addB;
sigCD = port(addAB, \A); sigCD = port(addAB, \A);
sigCD_signed = param(addAB, \A_SIGNED).as_bool(); sigCD.extend_u0(32, param(addAB, \A_SIGNED).as_bool());
} }
if (addAB) { if (addAB) {
int natural_mul_width = GetSize(sigA) + GetSize(sigB); int natural_mul_width = GetSize(sigA) + GetSize(sigB);
@ -155,7 +155,7 @@ match ffO_hi
optional optional
endmatch endmatch
code clock clock_pol sigO sigCD sigCD_signed code clock clock_pol sigO sigCD
if (ffO_lo || ffO_hi) { if (ffO_lo || ffO_hi) {
if (ffO_lo) { if (ffO_lo) {
SigBit c = port(ffO_lo, \CLK).as_bit(); SigBit c = port(ffO_lo, \CLK).as_bit();
@ -195,7 +195,7 @@ code clock clock_pol sigO sigCD sigCD_signed
else if (muxB) else if (muxB)
sigCD = port(muxAB, \A); sigCD = port(muxAB, \A);
else log_abort(); else log_abort();
sigCD_signed = addAB && param(addAB, \A_SIGNED).as_bool() && param(addAB, \B_SIGNED).as_bool(); sigCD.extend_u0(32, addAB && param(addAB, \A_SIGNED).as_bool() && param(addAB, \B_SIGNED).as_bool());
} }
} }
endcode endcode