From e19d33b003702a03b191fa2eda14d016a6bce0aa Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 1 Aug 2019 12:44:56 -0700
Subject: [PATCH] Cope with sign extension in mul2dsp

---
 passes/pmgen/ice40_dsp.cc  | 16 ++++++++--------
 passes/pmgen/ice40_dsp.pmg | 12 ++++++------
 2 files changed, 14 insertions(+), 14 deletions(-)

diff --git a/passes/pmgen/ice40_dsp.cc b/passes/pmgen/ice40_dsp.cc
index f88cd62dd..f6ae3a13f 100644
--- a/passes/pmgen/ice40_dsp.cc
+++ b/passes/pmgen/ice40_dsp.cc
@@ -72,17 +72,17 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 	pm.module->swap_names(cell, st.mul);
 
 	// SB_MAC16 Input Interface
-	bool a_signed = st.mul->getParam("\\A_SIGNED").as_bool();
-	bool b_signed = st.mul->getParam("\\B_SIGNED").as_bool();
-
 	SigSpec A = st.sigA;
-	A.extend_u0(16, a_signed);
+	log_assert(GetSize(A) == 16);
 
 	SigSpec B = st.sigB;
-	B.extend_u0(16, b_signed);
+	log_assert(GetSize(B) == 16);
 
 	SigSpec CD = st.sigCD;
-	CD.extend_u0(32, st.sigCD_signed);
+	if (CD.empty())
+		CD = RTLIL::Const(0, 32);
+	else
+		log_assert(GetSize(CD) == 32);
 
 	cell->setPort("\\A", A);
 	cell->setPort("\\B", B);
@@ -217,8 +217,8 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 	cell->setParam("\\BOTADDSUB_CARRYSELECT", Const(0, 2));
 
 	cell->setParam("\\MODE_8x8", State::S0);
-	cell->setParam("\\A_SIGNED", a_signed);
-	cell->setParam("\\B_SIGNED", b_signed);
+	cell->setParam("\\A_SIGNED", st.mul->getParam("\\A_SIGNED").as_bool());
+	cell->setParam("\\B_SIGNED", st.mul->getParam("\\B_SIGNED").as_bool());
 
 	pm.autoremove(st.mul);
 	pm.autoremove(st.ffH);
diff --git a/passes/pmgen/ice40_dsp.pmg b/passes/pmgen/ice40_dsp.pmg
index 73439cfd9..040332539 100644
--- a/passes/pmgen/ice40_dsp.pmg
+++ b/passes/pmgen/ice40_dsp.pmg
@@ -1,7 +1,7 @@
 pattern ice40_dsp
 
 state <SigBit> clock
-state <bool> clock_pol sigCD_signed
+state <bool> clock_pol
 state <SigSpec> sigA sigB sigCD sigH sigO
 state <Cell*> addAB muxAB
 
@@ -94,16 +94,16 @@ match addB
 	optional
 endmatch
 
-code addAB sigCD sigCD_signed sigO
+code addAB sigCD sigO
 	if (addA) {
 		addAB = addA;
 		sigCD = port(addAB, \B);
-		sigCD_signed = param(addAB, \B_SIGNED).as_bool();
+                sigCD.extend_u0(32, param(addAB, \B_SIGNED).as_bool());
 	}
 	if (addB) {
 		addAB = addB;
 		sigCD = port(addAB, \A);
-		sigCD_signed = param(addAB, \A_SIGNED).as_bool();
+                sigCD.extend_u0(32, param(addAB, \A_SIGNED).as_bool());
 	}
 	if (addAB) {
 		int natural_mul_width = GetSize(sigA) + GetSize(sigB);
@@ -155,7 +155,7 @@ match ffO_hi
 	optional
 endmatch
 
-code clock clock_pol sigO sigCD sigCD_signed
+code clock clock_pol sigO sigCD
 	if (ffO_lo || ffO_hi) {
 		if (ffO_lo) {
 			SigBit c = port(ffO_lo, \CLK).as_bit();
@@ -195,7 +195,7 @@ code clock clock_pol sigO sigCD sigCD_signed
 			else if (muxB)
 				sigCD = port(muxAB, \A);
 			else log_abort();
-			sigCD_signed = addAB && param(addAB, \A_SIGNED).as_bool() && param(addAB, \B_SIGNED).as_bool();
+                        sigCD.extend_u0(32, addAB && param(addAB, \A_SIGNED).as_bool() && param(addAB, \B_SIGNED).as_bool());
 		}
 	}
 endcode